aisair
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/analogin_api.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/analogin_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/cmsis_nvic.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/cmsis_nvic.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/gpio_api.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/gpio_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/gpio_irq_api.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/gpio_irq_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/i2c_api.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/i2c_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/mbed.ar
1.56 KB b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/mbed.ar
1.56 KB
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/mbed_board.o
8 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/mbed_board.o
8 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/mbed_retarget.o
29.2 KB b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/mbed_retarget.o
29.2 KB
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/pinmap.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/pinmap.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/port_api.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/port_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/pwmout_api.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/pwmout_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/retarget.o
-34.1 KB b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/retarget.o
-34.1 KB
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/serial_api.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/serial_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/sleep.o
16 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/sleep.o
16 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/spi_api.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/spi_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/sys.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/sys.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/system_nrf51.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/system_nrf51.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/twi_master.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/twi_master.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/us_ticker.o
0 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_ARM_STD/us_ticker.o
0 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_GCC_ARM/libmbed.a
422 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_GCC_ARM/libmbed.a
422 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_GCC_ARM/mbed_board.o
-4 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_GCC_ARM/mbed_board.o
-4 Bytes
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_GCC_ARM/mbed_retarget.o
13.7 KB b/‎TARGET_ARCH_BLE/TOOLCHAIN_GCC_ARM/mbed_retarget.o
13.7 KB
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_GCC_ARM/retarget.o
-14.7 KB b/‎TARGET_ARCH_BLE/TOOLCHAIN_GCC_ARM/retarget.o
-14.7 KB
diff --git a/‎TARGET_ARCH_BLE/TOOLCHAIN_GCC_ARM/sleep.o
16 Bytes b/‎TARGET_ARCH_BLE/TOOLCHAIN_GCC_ARM/sleep.o
16 Bytes
diff --git a/‎TARGET_ARCH_BLE/core_cmSecureAccess.h
Lines changed: 8 additions & 8 deletions b/‎TARGET_ARCH_BLE/core_cmSecureAccess.h
Lines changed: 8 additions & 8 deletions
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/PeripheralPins.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/PeripheralPins.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/analogin_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/analogin_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/gpio_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/gpio_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/gpio_irq_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/gpio_irq_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/i2c_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/i2c_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/mbed.ar
328 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/mbed.ar
328 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/mbed_board.o
8 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/mbed_board.o
8 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/mbed_retarget.o
28.1 KB b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/mbed_retarget.o
28.1 KB
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/pinmap.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/pinmap.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/port_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/port_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/pwmout_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/pwmout_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/retarget.o
-33 KB b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/retarget.o
-33 KB
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/serial_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/serial_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/sleep.o
20 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/sleep.o
20 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/spi_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/spi_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/sys.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/sys.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/system_LPC11Uxx.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/system_LPC11Uxx.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/us_ticker.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_MICRO/us_ticker.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/PeripheralPins.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/PeripheralPins.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/analogin_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/analogin_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/cmsis_nvic.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/cmsis_nvic.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/gpio_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/gpio_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/gpio_irq_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/gpio_irq_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/i2c_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/i2c_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/mbed.ar
272 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/mbed.ar
272 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/mbed_board.o
8 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/mbed_board.o
8 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/mbed_retarget.o
27.9 KB b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/mbed_retarget.o
27.9 KB
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/pinmap.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/pinmap.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/port_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/port_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/pwmout_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/pwmout_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/retarget.o
-32.8 KB b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/retarget.o
-32.8 KB
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/serial_api.o
4 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/serial_api.o
4 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/sleep.o
24 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/sleep.o
24 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/spi_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/spi_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/sys.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/sys.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/system_LPC11Uxx.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/system_LPC11Uxx.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/us_ticker.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_ARM_STD/us_ticker.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_GCC_ARM/libmbed.a
422 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_GCC_ARM/libmbed.a
422 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_GCC_ARM/mbed_board.o
-4 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_GCC_ARM/mbed_board.o
-4 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_GCC_ARM/mbed_retarget.o
13.7 KB b/‎TARGET_ARCH_GPRS/TOOLCHAIN_GCC_ARM/mbed_retarget.o
13.7 KB
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_GCC_ARM/retarget.o
-14.7 KB b/‎TARGET_ARCH_GPRS/TOOLCHAIN_GCC_ARM/retarget.o
-14.7 KB
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_GCC_ARM/sleep.o
16 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_GCC_ARM/sleep.o
16 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/PeripheralPins.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/PeripheralPins.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/analogin_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/analogin_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/cmain.o
164 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/cmain.o
164 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/cmsis_nvic.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/cmsis_nvic.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/gpio_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/gpio_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/gpio_irq_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/gpio_irq_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/i2c_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/i2c_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/mbed.a
4.75 KB b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/mbed.a
4.75 KB
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/mbed_board.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/mbed_board.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/mbed_retarget.o
22 KB b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/mbed_retarget.o
22 KB
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/pinmap.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/pinmap.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/port_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/port_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/pwmout_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/pwmout_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/retarget.o
-26.4 KB b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/retarget.o
-26.4 KB
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/serial_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/serial_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/sleep.o
8 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/sleep.o
8 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/spi_api.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/spi_api.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/system_LPC11Uxx.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/system_LPC11Uxx.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/us_ticker.o
0 Bytes b/‎TARGET_ARCH_GPRS/TOOLCHAIN_IAR/us_ticker.o
0 Bytes
diff --git a/‎TARGET_ARCH_GPRS/core_cmSecureAccess.h
Lines changed: 8 additions & 8 deletions b/‎TARGET_ARCH_GPRS/core_cmSecureAccess.h
Lines changed: 8 additions & 8 deletions
diff --git a/‎TARGET_ARCH_MAX/TARGET_STM/PinNamesTypes.h
Lines changed: 102 additions & 37 deletions b/‎TARGET_ARCH_MAX/TARGET_STM/PinNamesTypes.h
Lines changed: 102 additions & 37 deletions
diff --git a/‎TARGET_ARCH_MAX/TARGET_STM/TARGET_STM32F4/can_device.h
Lines changed: 53 additions & 0 deletions b/‎TARGET_ARCH_MAX/TARGET_STM/TARGET_STM32F4/can_device.h
Lines changed: 53 additions & 0 deletions
@@ -53,15 +53,15 @@
  * @param value[in]    Value to write at the address location.
  */
 #define SECURE_WRITE(address, value) \
-    uvisor_write(main, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL)
+    uvisor_write(public_box, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL)
 
 /** Get the value at the target address.
  *
  * @param address[in]  Target address
  * @returns The value `*address`.
  */
 #define SECURE_READ(address) \
-    uvisor_read(main, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL)
+    uvisor_read(public_box, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL)
 
 /** Get the selected bits at the target address.
  *
@@ -70,7 +70,7 @@
  * @returns The value `*address & mask`.
  */
 #define SECURE_BITS_GET(address, mask) \
-    UVISOR_BITS_GET(main, UVISOR_RGW_SHARED, address, mask)
+    UVISOR_BITS_GET(public_box, UVISOR_RGW_SHARED, address, mask)
 
 /** Check the selected bits at the target address.
  *
@@ -79,7 +79,7 @@
  * @returns The value `((*address & mask) == mask)`.
  */
 #define SECURE_BITS_CHECK(address, mask) \
-    UVISOR_BITS_CHECK(main, UVISOR_RGW_SHARED, address, mask)
+    UVISOR_BITS_CHECK(public_box, UVISOR_RGW_SHARED, address, mask)
 
 /** Set the selected bits to 1 at the target address.
  *
@@ -88,7 +88,7 @@
  * @param mask[in]     Bits to select out of the target address
  */
 #define SECURE_BITS_SET(address, mask) \
-    UVISOR_BITS_SET(main, UVISOR_RGW_SHARED, address, mask)
+    UVISOR_BITS_SET(public_box, UVISOR_RGW_SHARED, address, mask)
 
 /** Clear the selected bits at the target address.
  *
@@ -97,7 +97,7 @@
  * @param mask[in]     Bits to select out of the target address
  */
 #define SECURE_BITS_CLEAR(address, mask) \
-    UVISOR_BITS_CLEAR(main, UVISOR_RGW_SHARED, address, mask)
+    UVISOR_BITS_CLEAR(public_box, UVISOR_RGW_SHARED, address, mask)
 
 /** Set the selected bits at the target address to the given value.
  *
@@ -108,7 +108,7 @@
  *                     must be already shifted to the correct bit position
  */
 #define SECURE_BITS_SET_VALUE(address, mask, value) \
-    UVISOR_BITS_SET_VALUE(main, UVISOR_RGW_SHARED, address, mask, value)
+    UVISOR_BITS_SET_VALUE(public_box, UVISOR_RGW_SHARED, address, mask, value)
 
 /** Toggle the selected bits at the target address.
  *
@@ -117,7 +117,7 @@
  * @param mask[in]     Bits to select out of the target address
  */
 #define SECURE_BITS_TOGGLE(address, mask) \
-    UVISOR_BITS_TOGGLE(main, UVISOR_RGW_SHARED, address, mask)
+    UVISOR_BITS_TOGGLE(public_box, UVISOR_RGW_SHARED, address, mask)
 
 #else
 
 
@@ -53,15 +53,15 @@
  * @param value[in]    Value to write at the address location.
  */
 #define SECURE_WRITE(address, value) \
-    uvisor_write(main, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL)
+    uvisor_write(public_box, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL)
 
 /** Get the value at the target address.
  *
  * @param address[in]  Target address
  * @returns The value `*address`.
  */
 #define SECURE_READ(address) \
-    uvisor_read(main, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL)
+    uvisor_read(public_box, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL)
 
 /** Get the selected bits at the target address.
  *
@@ -70,7 +70,7 @@
  * @returns The value `*address & mask`.
  */
 #define SECURE_BITS_GET(address, mask) \
-    UVISOR_BITS_GET(main, UVISOR_RGW_SHARED, address, mask)
+    UVISOR_BITS_GET(public_box, UVISOR_RGW_SHARED, address, mask)
 
 /** Check the selected bits at the target address.
  *
@@ -79,7 +79,7 @@
  * @returns The value `((*address & mask) == mask)`.
  */
 #define SECURE_BITS_CHECK(address, mask) \
-    UVISOR_BITS_CHECK(main, UVISOR_RGW_SHARED, address, mask)
+    UVISOR_BITS_CHECK(public_box, UVISOR_RGW_SHARED, address, mask)
 
 /** Set the selected bits to 1 at the target address.
  *
@@ -88,7 +88,7 @@
  * @param mask[in]     Bits to select out of the target address
  */
 #define SECURE_BITS_SET(address, mask) \
-    UVISOR_BITS_SET(main, UVISOR_RGW_SHARED, address, mask)
+    UVISOR_BITS_SET(public_box, UVISOR_RGW_SHARED, address, mask)
 
 /** Clear the selected bits at the target address.
  *
@@ -97,7 +97,7 @@
  * @param mask[in]     Bits to select out of the target address
  */
 #define SECURE_BITS_CLEAR(address, mask) \
-    UVISOR_BITS_CLEAR(main, UVISOR_RGW_SHARED, address, mask)
+    UVISOR_BITS_CLEAR(public_box, UVISOR_RGW_SHARED, address, mask)
 
 /** Set the selected bits at the target address to the given value.
  *
@@ -108,7 +108,7 @@
  *                     must be already shifted to the correct bit position
  */
 #define SECURE_BITS_SET_VALUE(address, mask, value) \
-    UVISOR_BITS_SET_VALUE(main, UVISOR_RGW_SHARED, address, mask, value)
+    UVISOR_BITS_SET_VALUE(public_box, UVISOR_RGW_SHARED, address, mask, value)
 
 /** Toggle the selected bits at the target address.
  *
@@ -117,7 +117,7 @@
  * @param mask[in]     Bits to select out of the target address
  */
 #define SECURE_BITS_TOGGLE(address, mask) \
-    UVISOR_BITS_TOGGLE(main, UVISOR_RGW_SHARED, address, mask)
+    UVISOR_BITS_TOGGLE(public_box, UVISOR_RGW_SHARED, address, mask)
 
 #else
 
 
@@ -36,58 +36,123 @@
 extern "C" {
 #endif
 
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((MODE  & 0x0F) << 0) |\
-                                                ((PUPD  & 0x07) << 4) |\
-                                                ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((MODE     & 0x0F) <<  0) |\
-                                                                       ((PUPD     & 0x07) <<  4) |\
-                                                                       ((AFNUM    & 0x0F) <<  7) |\
-                                                                       ((CHANNEL  & 0x1F) << 11) |\
-                                                                       ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT              (0)
-#define STM_MODE_OUTPUT_PP          (1)
-#define STM_MODE_OUTPUT_OD          (2)
-#define STM_MODE_AF_PP              (3)
-#define STM_MODE_AF_OD              (4)
-#define STM_MODE_ANALOG             (5)
-#define STM_MODE_IT_RISING          (6)
-#define STM_MODE_IT_FALLING         (7)
-#define STM_MODE_IT_RISING_FALLING  (8)
-#define STM_MODE_EVT_RISING         (9)
-#define STM_MODE_EVT_FALLING        (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET       (12)
-// The last mode is only valid for specific families, so we put it in the end
-#define STM_MODE_ANALOG_ADC_CONTROL (13)
+/*  STM PIN data as used in pin_function is coded on 32 bits as below
+ *   [2:0]  Function (like in MODER reg) : Input / Output / Alt / Analog 
+ *     [3]  Output Push-Pull / Open Drain (as in OTYPER reg)
+ *   [5:4]  as in PUPDR reg: No Pull, Pull-up, Pull-Donc
+ *   [7:6]  Reserved for speed config (as in OSPEEDR), but not used yet
+ *  [11:8]  Alternate Num (as in AFRL/AFRG reg)
+ * [16:12]  Channel (Analog/Timer specific)
+ *    [17]  Inverted (Analog/Timer specific)
+ *    [18]  Analog ADC control - Only valid for specific families
+ * [32:19]  Reserved
+ */
+
+#define STM_PIN_FUNCTION_MASK 0x07
+#define STM_PIN_FUNCTION_SHIFT 0
+#define STM_PIN_FUNCTION_BITS (STM_PIN_FUNCTION_MASK << STM_PIN_FUNCTION_SHIFT)
+
+#define STM_PIN_OD_MASK 0x01
+#define STM_PIN_OD_SHIFT 3
+#define STM_PIN_OD_BITS (STM_PIN_OD_MASK << STM_PIN_OD_SHIFT)
+
+#define STM_PIN_PUPD_MASK 0x03
+#define STM_PIN_PUPD_SHIFT 4
+#define STM_PIN_PUPD_BITS (STM_PIN_PUPD_MASK << STM_PIN_PUPD_SHIFT)
+
+#define STM_PIN_SPEED_MASK 0x03
+#define STM_PIN_SPEED_SHIFT 6
+#define STM_PIN_SPEED_BITS (STM_PIN_SPEED_MASK << STM_PIN_SPEED_SHIFT)
+
+#define STM_PIN_AFNUM_MASK 0x0F
+#define STM_PIN_AFNUM_SHIFT 8
+#define STM_PIN_AFNUM_BITS (STM_PIN_AFNUM_MASK << STM_PIN_AFNUM_SHIFT)
+
+#define STM_PIN_CHAN_MASK 0x1F
+#define STM_PIN_CHAN_SHIFT 12
+#define STM_PIN_CHANNEL_BIT (STM_PIN_CHAN_MASK << STM_PIN_CHAN_SHIFT)
+
+#define STM_PIN_INV_MASK 0x01
+#define STM_PIN_INV_SHIFT 17
+#define STM_PIN_INV_BIT (STM_PIN_INV_MASK << STM_PIN_INV_SHIFT)
+
+#define STM_PIN_AN_CTRL_MASK 0x01
+#define STM_PIN_AN_CTRL_SHIFT 18
+#define STM_PIN_ANALOG_CONTROL_BIT (STM_PIN_AN_CTRL_MASK << STM_PIN_AN_CTRL_SHIFT)
+
+#define STM_PIN_FUNCTION(X)         (((X) >> STM_PIN_FUNCTION_SHIFT) & STM_PIN_FUNCTION_MASK)
+#define STM_PIN_OD(X)               (((X) >> STM_PIN_OD_SHIFT) & STM_PIN_OD_MASK)
+#define STM_PIN_PUPD(X)             (((X) >> STM_PIN_PUPD_SHIFT) & STM_PIN_PUPD_MASK)
+#define STM_PIN_SPEED(X)            (((X) >> STM_PIN_SPEED_SHIFT) & STM_PIN_SPEED_MASK)
+#define STM_PIN_AFNUM(X)            (((X) >> STM_PIN_AFNUM_SHIFT) & STM_PIN_AFNUM_MASK)
+#define STM_PIN_CHANNEL(X)          (((X) >> STM_PIN_CHAN_SHIFT) & STM_PIN_CHAN_MASK)
+#define STM_PIN_INVERTED(X)         (((X) >> STM_PIN_INV_SHIFT) & STM_PIN_INV_MASK)
+#define STM_PIN_ANALOG_CONTROL(X)   (((X) >> STM_PIN_AN_CTRL_SHIFT) & STM_PIN_AN_CTRL_MASK)
+
+#define STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM)  ((int)(FUNC_OD) |\
+                          ((PUPD  & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
+                          ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT))
+
+#define STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV) \
+                                            ((int)(FUNC_OD) |\
+                       ((PUPD   & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
+                       ((AFNUM  & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\
+                       ((CHAN   & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\
+                       ((INV    & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT))
+
+/*
+ * MACROS to support the legacy definition of PIN formats
+ * The STM_MODE_ defines contain the function and the Push-pull/OpenDrain
+ * configuration (legacy inheritance).
+ */
+#define STM_PIN_DATA(FUNC_OD, PUPD, AFNUM) \
+            STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM)
+#define STM_PIN_DATA_EXT(FUNC_OD, PUPD, AFNUM, CHANNEL, INVERTED) \
+            STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHANNEL, INVERTED)
+
+typedef enum {
+    STM_PIN_INPUT = 0,
+    STM_PIN_OUTPUT = 1,
+    STM_PIN_ALTERNATE = 2,
+    STM_PIN_ANALOG = 3,
+} StmPinFunction;
+
+#define STM_MODE_INPUT               (STM_PIN_INPUT)
+#define STM_MODE_OUTPUT_PP           (STM_PIN_OUTPUT)
+#define STM_MODE_OUTPUT_OD           (STM_PIN_OUTPUT | STM_PIN_OD_BITS)
+#define STM_MODE_AF_PP               (STM_PIN_ALTERNATE)
+#define STM_MODE_AF_OD               (STM_PIN_ALTERNATE | STM_PIN_OD_BITS)
+#define STM_MODE_ANALOG              (STM_PIN_ANALOG)
+#define STM_MODE_ANALOG_ADC_CONTROL  (STM_PIN_ANALOG | STM_PIN_ANALOG_CONTROL_BIT)
 
 // High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
 // Low nibble  = pin number
 #define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
 #define STM_PIN(X)  ((uint32_t)(X) & 0xF)
 
+/*  Defines to be used by application */
 typedef enum {
-    PIN_INPUT,
+    PIN_INPUT = 0,
     PIN_OUTPUT
 } PinDirection;
 
 typedef enum {
-    PullNone  = 0,
-    PullUp    = 1,
-    PullDown  = 2,
-    OpenDrain = 3,
-    PullDefault = PullNone
+    PullNone          = 0,
+    PullUp            = 1,
+    PullDown          = 2,
+    OpenDrainPullUp   = 3,
+    OpenDrainNoPull   = 4,
+    OpenDrainPullDown = 5,
+    PushPullNoPull    = PullNone,
+    PushPullPullUp    = PullUp,
+    PushPullPullDown  = PullDown,
+    OpenDrain         = OpenDrainPullUp,
+    PullDefault       = PullNone
 } PinMode;
 
 #ifdef __cplusplus
 }
 #endif
 
 #endif
+
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_DEVICE_H
+#define MBED_CAN_DEVICE_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef DEVICE_CAN
+
+#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie (1 or 2)
+
+#define CAN1_IRQ_RX_IRQN        CAN1_RX0_IRQn
+#define CAN1_IRQ_RX_VECT        CAN1_RX0_IRQHandler
+#define CAN1_IRQ_TX_IRQN        CAN1_TX_IRQn
+#define CAN1_IRQ_TX_VECT        CAN1_TX_IRQHandler
+#define CAN1_IRQ_ERROR_IRQN     CAN1_SCE_IRQn
+#define CAN1_IRQ_ERROR_VECT     CAN1_SCE_IRQHandler
+#define CAN1_IRQ_PASSIVE_IRQN   CAN1_SCE_IRQn
+#define CAN1_IRQ_PASSIVE_VECT   CAN1_SCE_IRQHandler
+#define CAN1_IRQ_BUS_IRQN       CAN1_SCE_IRQn
+#define CAN1_IRQ_BUS_VECT       CAN1_SCE_IRQHandler
+
+#define CAN2_IRQ_RX_IRQN        CAN2_RX0_IRQn
+#define CAN2_IRQ_RX_VECT        CAN2_RX0_IRQHandler
+#define CAN2_IRQ_TX_IRQN        CAN2_TX_IRQn
+#define CAN2_IRQ_TX_VECT        CAN2_TX_IRQHandler
+#define CAN2_IRQ_ERROR_IRQN     CAN2_SCE_IRQn
+#define CAN2_IRQ_ERROR_VECT     CAN2_SCE_IRQHandler
+#define CAN2_IRQ_PASSIVE_IRQN   CAN2_SCE_IRQn
+#define CAN2_IRQ_PASSIVE_VECT   CAN2_SCE_IRQHandler
+#define CAN2_IRQ_BUS_IRQN       CAN2_SCE_IRQn
+#define CAN2_IRQ_BUS_VECT       CAN2_SCE_IRQHandler
+
+#endif // DEVICE_CAN
+
+#endif