STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) #3843
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How was this tested? |
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I checked the SPI clock with a scope on L476RG device. |
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Good morning, I tested the change by embedding it into my development. My SPI Winbond flash works as expected: The change works fine for me. @bcostm (off topic), I did an code enhancements in the STM HAL_SPI_TransmitReceive function. It is not much, how can I provide my change to you/STM? |
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Thanks Helmut for the testing. Concerning you HAL SPI change, please send a PR and we'll have a look into it. Thanks. |
bcostm
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Ports for Upcoming Targets Fixes and Changes 3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files ARMmbed/mbed-os#3716 3741: STM32 remove warning in hal_tick_32b.c file ARMmbed/mbed-os#3741 3780: STM32L4 : Fix GPIO G port compatibility ARMmbed/mbed-os#3780 3831: NCS36510: SPISLAVE enabled (Conflict resolved) ARMmbed/mbed-os#3831 3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os ARMmbed/mbed-os#3836 3840: STM32: gpio SPEED - always set High Speed by default ARMmbed/mbed-os#3840 3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) ARMmbed/mbed-os#3844 3850: STM32: change spi error to debug warning ARMmbed/mbed-os#3850 3860: Define GPIO_IP_WITHOUT_BRR for xDot platform ARMmbed/mbed-os#3860 3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated ARMmbed/mbed-os#3880 3795: Fix pwm period calc ARMmbed/mbed-os#3795 3828: STM32 CAN API: correct format and type ARMmbed/mbed-os#3828 3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization ARMmbed/mbed-os#3842 3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) ARMmbed/mbed-os#3843 3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. ARMmbed/mbed-os#3879 3902: Fix heap and stack size for NUCLEO_F746ZG ARMmbed/mbed-os#3902 3829: can_write(): return error code when no tx mailboxes are available ARMmbed/mbed-os#3829
Description
The APB2 clock was not set to the maximum possible value (80 MHz). The SPI clock can now go up to 40 MHz.
Discussion started in Issue #3735.
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READY
Migrations
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