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[mips] Range check simm16
Summary: There are too many instructions to exhaustively test so addiu and lwc2 are used as representative examples. It should be noted that many memory instructions that should have simm16 range checking do not because it is also necessary to support the macro of the same name which accepts simm32. The range checks for these occur in the macro expansion. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18437 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265019 91177308-0d34-0410-b5e6-96231b3b80d8
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9 files changed

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-49
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9 files changed

+86
-49
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‎lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -947,6 +947,15 @@ class MipsOperand : public MCParsedAsmOperand {
947947
Inst.addOperand(MCOperand::createImm(Imm));
948948
}
949949

950+
template <unsigned Bits>
951+
void addSImmOperands(MCInst &Inst, unsigned N) const {
952+
if (isImm() && !isConstantImm()) {
953+
addExpr(Inst, getImm());
954+
return;
955+
}
956+
addConstantSImmOperands<Bits, 0, 0>(Inst, N);
957+
}
958+
950959
template <unsigned Bits>
951960
void addUImmOperands(MCInst &Inst, unsigned N) const {
952961
if (isImm() && !isConstantImm()) {
@@ -1031,6 +1040,9 @@ class MipsOperand : public MCParsedAsmOperand {
10311040
template <unsigned Bits, int Offset = 0> bool isConstantUImm() const {
10321041
return isConstantImm() && isUInt<Bits>(getConstantImm() - Offset);
10331042
}
1043+
template <unsigned Bits> bool isSImm() const {
1044+
return isConstantImm() ? isInt<Bits>(getConstantImm()) : isImm();
1045+
}
10341046
template <unsigned Bits> bool isUImm() const {
10351047
return isConstantImm() ? isUInt<Bits>(getConstantImm()) : isImm();
10361048
}
@@ -3793,6 +3805,10 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
37933805
case Match_UImm16_Relaxed:
37943806
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
37953807
"expected 16-bit unsigned immediate");
3808+
case Match_SImm16:
3809+
case Match_SImm16_Relaxed:
3810+
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3811+
"expected 16-bit signed immediate");
37963812
case Match_UImm20_0:
37973813
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
37983814
"expected 20-bit unsigned immediate");
@@ -3820,6 +3836,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
38203836
case Match_MemSImm11:
38213837
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
38223838
"expected memory with 11-bit signed offset");
3839+
case Match_MemSImm16:
3840+
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3841+
"expected memory with 16-bit signed offset");
38233842
}
38243843

38253844
llvm_unreachable("Implement any new match types added!");

‎lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -373,11 +373,6 @@ static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
373373
uint64_t Address,
374374
const void *Decoder);
375375

376-
static DecodeStatus DecodeSimm16(MCInst &Inst,
377-
unsigned Insn,
378-
uint64_t Address,
379-
const void *Decoder);
380-
381376
template <unsigned Bits, int Offset, int Scale>
382377
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
383378
uint64_t Address,
@@ -1929,14 +1924,6 @@ static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
19291924
return MCDisassembler::Success;
19301925
}
19311926

1932-
static DecodeStatus DecodeSimm16(MCInst &Inst,
1933-
unsigned Insn,
1934-
uint64_t Address,
1935-
const void *Decoder) {
1936-
Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1937-
return MCDisassembler::Success;
1938-
}
1939-
19401927
template <unsigned Bits, int Offset, int Scale>
19411928
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
19421929
uint64_t Address,

‎lib/Target/Mips/Mips64r6InstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
4848

4949
class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
5050
dag OutOperandList = (outs GPROpnd:$rs);
51-
dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
51+
dag InOperandList = (ins GPROpnd:$rt, simm16_relaxed:$imm);
5252
string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
5353
string Constraints = "$rs = $rt";
5454
InstrItinClass Itinerary = itin;

‎lib/Target/Mips/MipsInstrInfo.td

Lines changed: 48 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -421,6 +421,15 @@ class ConstantUImmRangeAsmOperandClass<int Bottom, int Top,
421421
let DiagnosticType = "UImmRange" # Bottom # "_" # Top;
422422
}
423423

424+
class SImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
425+
: AsmOperandClass {
426+
let Name = "SImm" # Bits;
427+
let RenderMethod = "addSImmOperands<" # Bits # ">";
428+
let PredicateMethod = "isSImm<" # Bits # ">";
429+
let SuperClasses = Supers;
430+
let DiagnosticType = "SImm" # Bits;
431+
}
432+
424433
class UImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
425434
: AsmOperandClass {
426435
let Name = "UImm" # Bits;
@@ -465,11 +474,19 @@ def UImm16RelaxedAsmOperandClass
465474
}
466475
def UImm16AsmOperandClass
467476
: UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;
477+
def SImm16RelaxedAsmOperandClass
478+
: SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> {
479+
let Name = "SImm16_Relaxed";
480+
let PredicateMethod = "isAnyImm<16>";
481+
let DiagnosticType = "SImm16_Relaxed";
482+
}
483+
def SImm16AsmOperandClass
484+
: SImmAsmOperandClass<16, [SImm16RelaxedAsmOperandClass]>;
468485
def ConstantSImm10Lsl3AsmOperandClass : AsmOperandClass {
469486
let Name = "SImm10Lsl3";
470487
let RenderMethod = "addImmOperands";
471488
let PredicateMethod = "isScaledSImm<10, 3>";
472-
let SuperClasses = [UImm16AsmOperandClass];
489+
let SuperClasses = [SImm16AsmOperandClass];
473490
let DiagnosticType = "SImm10_Lsl3";
474491
}
475492
def ConstantSImm10Lsl2AsmOperandClass : AsmOperandClass {
@@ -600,10 +617,6 @@ def calltarget : Operand<iPTR> {
600617

601618
def imm64: Operand<i64>;
602619

603-
def simm16 : Operand<i32> {
604-
let DecoderMethod= "DecodeSimm16";
605-
}
606-
607620
def simm19_lsl2 : Operand<i32> {
608621
let EncoderMethod = "getSimm19Lsl2Encoding";
609622
let DecoderMethod = "DecodeSimm19Lsl2";
@@ -618,10 +631,6 @@ def simm18_lsl3 : Operand<i32> {
618631

619632
def simm32 : Operand<i32>;
620633

621-
def simm16_64 : Operand<i64> {
622-
let DecoderMethod = "DecodeSimm16";
623-
}
624-
625634
// Zero
626635
def uimmz : Operand<i32> {
627636
let PrintMethod = "printUImm<0>";
@@ -796,6 +805,22 @@ def simm7_lsl2 : Operand<OtherVT> {
796805
let ParserMatchClass = ConstantSImm7Lsl2AsmOperandClass;
797806
}
798807

808+
def simm16 : Operand<i32> {
809+
let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";
810+
let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass");
811+
}
812+
813+
// Like simm16 but coerces uimm16 to simm16.
814+
def simm16_relaxed : Operand<i32> {
815+
let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";
816+
let ParserMatchClass = !cast<AsmOperandClass>("SImm16RelaxedAsmOperandClass");
817+
}
818+
819+
def simm16_64 : Operand<i64> {
820+
let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";
821+
let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass");
822+
}
823+
799824
// This is almost the same as a uimm7 but 0x7f is interpreted as -1.
800825
def li16_imm : Operand<i32> {
801826
let DecoderMethod = "DecodeLi16Imm";
@@ -863,6 +888,7 @@ def MipsMemSimm16AsmOperand : AsmOperandClass {
863888
let RenderMethod = "addMemOperands";
864889
let ParserMethod = "parseMemOperand";
865890
let PredicateMethod = "isMemWithSimmOffset<16>";
891+
let DiagnosticType = "MemSImm16";
866892
}
867893

868894
def MipsInvertedImmoperand : AsmOperandClass {
@@ -1603,11 +1629,11 @@ def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
16031629

16041630
/// Arithmetic Instructions (ALU Immediate)
16051631
let AdditionalPredicates = [NotInMicroMips] in {
1606-
def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd,
1632+
def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
16071633
II_ADDIU, immSExt16, add>,
16081634
ADDI_FM<0x9>, IsAsCheapAsAMove;
16091635
}
1610-
def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1636+
def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd>, ADDI_FM<0x8>,
16111637
ISA_MIPS1_NOT_32R6_64R6;
16121638
def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
16131639
SLTI_FM<0xa>;
@@ -2115,19 +2141,19 @@ def : MipsInstAlias<"move $dst, $src",
21152141
def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
21162142
ISA_MIPS1_NOT_32R6_64R6;
21172143
def : MipsInstAlias<"addu $rs, $rt, $imm",
2118-
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
2144+
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
21192145
def : MipsInstAlias<"addu $rs, $imm",
2120-
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
2146+
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>;
21212147
def : MipsInstAlias<"add $rs, $rt, $imm",
2122-
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
2148+
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>,
21232149
ISA_MIPS1_NOT_32R6_64R6;
21242150
def : MipsInstAlias<"add $rs, $imm",
2125-
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
2151+
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>,
21262152
ISA_MIPS1_NOT_32R6_64R6;
21272153
def : MipsInstAlias<"and $rs, $rt, $imm",
2128-
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
2154+
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
21292155
def : MipsInstAlias<"and $rs, $imm",
2130-
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
2156+
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>;
21312157
def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
21322158
let Predicates = [NotInMicroMips] in {
21332159
def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
@@ -2142,9 +2168,9 @@ def : MipsInstAlias<"negu $rt",
21422168
def : MipsInstAlias<"negu $rt, $rs",
21432169
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
21442170
def : MipsInstAlias<"slt $rs, $rt, $imm",
2145-
(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
2171+
(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
21462172
def : MipsInstAlias<"sltu $rt, $rs, $imm",
2147-
(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
2173+
(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32:$imm), 0>;
21482174
def : MipsInstAlias<"xor $rs, $rt, $imm",
21492175
(XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
21502176
def : MipsInstAlias<"xor $rs, $imm",
@@ -2238,8 +2264,9 @@ def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
22382264
def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
22392265
"jal\t$rs"> ;
22402266

2241-
def NORImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
2242-
"nor\t$rs, $rt, $imm"> ;
2267+
def NORImm : MipsAsmPseudoInst<
2268+
(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm),
2269+
"nor\t$rs, $rt, $imm"> ;
22432270

22442271
let hasDelaySlot = 1, isCTI = 1 in {
22452272
def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),

‎test/MC/Mips/mips1/invalid-mips2-wrong-error.s

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@
77

88
.set noat
99
ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10-
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
11-
ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
10+
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
11+
ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
1212
ldc3 $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1313
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
1414
sc $t7,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
1515
sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
16-
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
17-
sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
16+
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
17+
sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
1818
sdc3 $12,5835($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

‎test/MC/Mips/mips1/invalid-mips3-wrong-error.s

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@
88
.set noat
99
ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1010
ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11-
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
12-
ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
11+
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
12+
ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
1313
ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1414
ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1515
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
@@ -19,7 +19,7 @@
1919
scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
2020
sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2121
sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
22-
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
23-
sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
22+
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
23+
sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
2424
sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2525
sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

‎test/MC/Mips/mips1/invalid-mips4-wrong-error.s

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,8 @@
1010
bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1111
ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1212
ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13-
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
14-
ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
13+
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
14+
ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
1515
ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1616
ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1717
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
@@ -21,7 +21,7 @@
2121
scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
2222
sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2323
sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
24-
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
25-
sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
24+
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
25+
sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
2626
sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2727
sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

‎test/MC/Mips/mips32r2/invalid.s

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,8 @@
66

77
.text
88
.set noreorder
9+
addiu $2, $3, -32769 # CHECK: :[[@LINE]]:23: error: expected 16-bit signed immediate
10+
addiu $2, $3, 65536 # CHECK: :[[@LINE]]:23: error: expected 16-bit signed immediate
911
andi $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
1012
andi $2, $3, 65536 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
1113
cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
@@ -20,6 +22,8 @@
2022
ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
2123
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
2224
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
25+
lwc2 $2, -32769($3) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
26+
lwc2 $2, 32768($3) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
2327
ori $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 16-bit unsigned immediate
2428
ori $2, $3, 65536 # CHECK: :[[@LINE]]:21: error: expected 16-bit unsigned immediate
2529
pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate

‎test/MC/Mips/mips64r6/valid.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,8 +105,8 @@ a:
105105
daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f]
106106
dahi $3,0x5678 # CHECK: dahi $3, 22136 # encoding: [0x04,0x66,0x56,0x78]
107107
dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64]
108-
dati $3,0xabcd # CHECK: dati $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd]
109-
daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34]
108+
dati $3,0xabcd # CHECK: dati $3, -21555 # encoding: [0x04,0x7e,0xab,0xcd]
109+
daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34]
110110
dbitswap $4, $2 # CHECK: dbitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x24]
111111
dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x00,0xc0,0x90,0x53]
112112
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]

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