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Commit 956cf76

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kitbartonkitbarton
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This reverts commit r265505.
Revert "[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance". This patch has caused a functional regression in SPEC2k6 namd, and a performance regression in mesa-pipe. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267927 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

Lines changed: 0 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -528,10 +528,6 @@ struct PPCOperand : public MCParsedAsmOperand {
528528
(Kind == Immediate && isInt<16>(getImm()) &&
529529
(getImm() & 3) == 0); }
530530
bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
531-
bool isD8RCRegNumber() const { return Kind == Immediate &&
532-
isUInt<5>(getImm()) &&
533-
// required even register id
534-
!(getImm() & 0x1); }
535531
bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
536532
bool isCCRegNumber() const { return (Kind == Expression
537533
&& isUInt<3>(getExprCRVal())) ||
@@ -594,11 +590,6 @@ struct PPCOperand : public MCParsedAsmOperand {
594590
Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
595591
}
596592

597-
void addRegD8RCOperands(MCInst &Inst, unsigned N) const {
598-
assert(N == 1 && "Invalid number of operands!");
599-
Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
600-
}
601-
602593
void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
603594
assert(N == 1 && "Invalid number of operands!");
604595
Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
@@ -1229,19 +1220,6 @@ void PPCAsmParser::ProcessInstruction(MCInst &Inst,
12291220
Inst = TmpInst;
12301221
break;
12311222
}
1232-
// ISA3.0 Instructions:
1233-
case PPC::SUBPCIS:
1234-
case PPC::LNIA: {
1235-
MCInst TmpInst;
1236-
TmpInst.setOpcode(PPC::ADDPCIS);
1237-
TmpInst.addOperand(Inst.getOperand(0));
1238-
if (Opcode == PPC::SUBPCIS)
1239-
addNegOperand(TmpInst, Inst.getOperand(1), getContext());
1240-
else
1241-
TmpInst.addOperand(MCOperand::createImm(0));
1242-
Inst = TmpInst;
1243-
break;
1244-
}
12451223
}
12461224
}
12471225

‎lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -242,12 +242,6 @@ static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
242242
return decodeRegisterClass(Inst, RegNo, FRegs);
243243
}
244244

245-
static DecodeStatus DecodeD8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
246-
uint64_t Address,
247-
const void *Decoder) {
248-
return decodeRegisterClass(Inst, RegNo, FRegs);
249-
}
250-
251245
static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
252246
uint64_t Address,
253247
const void *Decoder) {

‎lib/Target/PowerPC/PPCInstr64Bit.td

Lines changed: 0 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -1279,63 +1279,6 @@ def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>
12791279

12801280
let Predicates = [IsISA3_0] in {
12811281

1282-
// [PO RT RA RB RC XO]
1283-
class VA_RT5_RA5_RB5_RC5<bits<6> xo, string opc, InstrItinClass itin,
1284-
list<dag> pattern>
1285-
: VAForm_1a<xo, (outs g8rc:$rD), (ins g8rc:$rA, g8rc:$rB, g8rc:$rC),
1286-
!strconcat(opc, " $rD, $rA, $rB, $rC"), itin, pattern>;
1287-
1288-
// 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned/Low-DWord
1289-
def MADDHD : VA_RT5_RA5_RB5_RC5<48, "maddhd" , IIC_IntGeneral, []>;
1290-
def MADDHDU : VA_RT5_RA5_RB5_RC5<49, "maddhdu", IIC_IntGeneral, []>;
1291-
def MADDLD : VA_RT5_RA5_RB5_RC5<51, "maddld ", IIC_IntGeneral, []>;
1292-
1293-
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1294-
// Add PC Immediate Shifted
1295-
def ADDPCIS8 : DX_RD5_IM16<19, 2, (outs g8rc:$rD), (ins s16imm:$IMM),
1296-
"addpcis $rD, $IMM", IIC_IntSimple, []>;
1297-
1298-
// Modulo {Signed/Unsigned}-Word
1299-
def MODSW8 : X_RT5_RA5_RB5<779, "modsw", g8rc, IIC_IntDivW, []>;
1300-
def MODUW8 : X_RT5_RA5_RB5<267, "moduw", g8rc, IIC_IntDivW, []>;
1301-
}
1302-
1303-
// Modulo {Signed/Unsigned}-DWord
1304-
def MODSD : X_RT5_RA5_RB5<777, "modsd", g8rc, IIC_IntDivW, []>;
1305-
def MODUD : X_RT5_RA5_RB5<265, "modud", g8rc, IIC_IntDivW, []>;
1306-
1307-
// [PO RS RA sh XO sh Rc]
1308-
multiclass XS_RS5_RA5_SH5r<bits<6> opcode, bits<9> xo, string opc,
1309-
InstrItinClass itin, list<dag> pattern> {
1310-
let BaseName = opc in {
1311-
def NAME : XSForm_1<opcode, xo, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
1312-
!strconcat(opc, " $rA, $rS, $SH"), itin, pattern>;
1313-
let Defs = [CR0] in
1314-
def o : XSForm_1<opcode, xo, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
1315-
!strconcat(opc, ". $rA, $rS, $SH"), itin, pattern>,
1316-
isDOT;
1317-
}
1318-
}
1319-
1320-
// Deliver A Random Number
1321-
def DARN : X_RD5_L2<31, 755, (outs g8rc:$rD), (ins u2imm:$L), "darn $rD, $L",
1322-
IIC_IntGeneral, []>;
1323-
1324-
// Extend-Sign Word and Shift Left Immediate
1325-
defm EXTSWSLI : XS_RS5_RA5_SH5r<31, 445, "extswsli" , IIC_IntShift, []>;
1326-
1327-
// Set Boolean
1328-
def SETB : X_RD5_BFA3<31, 128, (outs g8rc:$rD), (ins u3imm:$BFA),
1329-
"setb $rD, $BFA", IIC_IntGeneral, []>;
1330-
1331-
// DFP Test Significance Immediate [Quad]
1332-
def DTSTSFI : X_BF3_IM6_RS5<59, 675,
1333-
(outs crbitrc:$BF), (ins u6imm:$UIM, f8rc:$FRB),
1334-
"dtstsfi $BF, $UIM, $FRB", IIC_FPGeneral, []>;
1335-
def DTSTSFIQ : X_BF3_IM6_RS5<63, 675,
1336-
(outs crbitrc:$BF), (ins u6imm:$UIM, d8rc:$FRBp),
1337-
"dtstsfiq $BF, $UIM, $FRBp", IIC_FPGeneral, []>;
1338-
13391282
class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
13401283
InstrItinClass itin, list<dag> pattern>
13411284
: X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),

‎lib/Target/PowerPC/PPCInstrFormats.td

Lines changed: 0 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -376,23 +376,6 @@ class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
376376
let Inst{29-31} = xo;
377377
}
378378

379-
// DX-Form: [PO RT d1 d0 XO d2]
380-
class DX_RD5_IM16<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
381-
InstrItinClass itin, list<dag> pattern>
382-
: I<opcode, OOL, IOL, asmstr, itin> {
383-
bits<5> RD;
384-
bits<16> IMM;
385-
386-
let Pattern = pattern;
387-
388-
let Inst{6-10} = RD;
389-
// IMM = d0 || d1 || d2
390-
let Inst{11-15} = IMM{5-1}; // d1
391-
let Inst{16-25} = IMM{15-6}; // d0
392-
let Inst{26-30} = xo;
393-
let Inst{31} = IMM{0}; // d2
394-
}
395-
396379
// 1.7.6 X-Form
397380
class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
398381
InstrItinClass itin, list<dag> pattern>
@@ -780,11 +763,6 @@ class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
780763
}
781764

782765
// [PO RT RA RB XO /]
783-
class X_RT5_RA5_RB5<bits<10> xo, string opc, RegisterOperand type,
784-
InstrItinClass itin, list<dag> pattern>
785-
: XForm_base_r3xo<31, xo, (outs type:$rD), (ins type:$rA, type:$rB),
786-
!strconcat(opc, " $rD, $rA, $rB"), itin, pattern>;
787-
788766
class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
789767
string asmstr, InstrItinClass itin, list<dag> pattern>
790768
: I<opcode, OOL, IOL, asmstr, itin> {
@@ -829,57 +807,6 @@ class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
829807
let A = xo2;
830808
}
831809

832-
// [PO RT /// L /// XO /]
833-
class X_RD5_L2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
834-
InstrItinClass itin, list<dag> pattern>
835-
: I<opcode, OOL, IOL, asmstr, itin> {
836-
bits<5> RD;
837-
bits<2> L;
838-
839-
let Pattern = pattern;
840-
841-
let Inst{6-10} = RD;
842-
let Inst{11-13} = 0;
843-
let Inst{14-15} = L;
844-
let Inst{16-20} = 0;
845-
let Inst{21-30} = xo;
846-
let Inst{31} = 0;
847-
}
848-
849-
// [PO RT BFA // /// XO /]
850-
class X_RD5_BFA3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
851-
InstrItinClass itin, list<dag> pattern>
852-
: I<opcode, OOL, IOL, asmstr, itin> {
853-
bits<5> RD;
854-
bits<3> BFA;
855-
856-
let Pattern = pattern;
857-
858-
let Inst{6-10} = RD;
859-
let Inst{11-13} = BFA;
860-
let Inst{14-20} = 0;
861-
let Inst{21-30} = xo;
862-
let Inst{31} = 0;
863-
}
864-
865-
// [PO BF / UIM FRB XO /] or [PO BF / UIM FRBp XO /]
866-
class X_BF3_IM6_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
867-
string asmstr, InstrItinClass itin, list<dag> pattern>
868-
: I<opcode, OOL, IOL, asmstr, itin> {
869-
bits<3> BF;
870-
bits<6> UIM;
871-
bits<5> FRB;
872-
873-
let Pattern = pattern;
874-
875-
let Inst{6-8} = BF;
876-
let Inst{9} = 0;
877-
let Inst{10-15} = UIM;
878-
let Inst{16-20} = FRB;
879-
let Inst{21-30} = xo;
880-
let Inst{31} = 0;
881-
}
882-
883810
class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
884811
string asmstr, InstrItinClass itin, list<dag> pattern>
885812
: I<opcode, OOL, IOL, asmstr, itin> {

‎lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -423,12 +423,6 @@ def PPCRegF4RCAsmOperand : AsmOperandClass {
423423
def f4rc : RegisterOperand<F4RC> {
424424
let ParserMatchClass = PPCRegF4RCAsmOperand;
425425
}
426-
def PPCRegD8RCAsmOperand : AsmOperandClass {
427-
let Name = "RegD8RC"; let PredicateMethod = "isD8RCRegNumber";
428-
}
429-
def d8rc : RegisterOperand<D8RC> {
430-
let ParserMatchClass = PPCRegD8RCAsmOperand;
431-
}
432426
def PPCRegVRRCAsmOperand : AsmOperandClass {
433427
let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
434428
}
@@ -4201,17 +4195,6 @@ def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
42014195

42024196
let Predicates = [IsISA3_0] in {
42034197

4204-
// Add PC Immediate Shifted
4205-
def ADDPCIS : DX_RD5_IM16<19, 2, (outs gprc:$rD), (ins s16imm:$IMM),
4206-
"addpcis $rD, $IMM", IIC_IntSimple, []>;
4207-
// Extended Mnemonics of ADDPCIS
4208-
def SUBPCIS : PPCAsmPseudo<"subpcis $rD, $IMM", (ins gprc:$rD, s16imm:$IMM)>;
4209-
def LNIA : PPCAsmPseudo<"lnia $rD", (ins gprc:$rD)>;
4210-
4211-
// Modulo {Signed/Unsigned}-Word
4212-
def MODSW : X_RT5_RA5_RB5<779, "modsw", gprc, IIC_IntDivW, []>;
4213-
def MODUW : X_RT5_RA5_RB5<267, "moduw", gprc, IIC_IntDivW, []>;
4214-
42154198
// Copy-Paste Facility
42164199
// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to
42174200
// PASTE for naming consistency.

‎lib/Target/PowerPC/PPCRegisterInfo.td

Lines changed: 0 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,6 @@ def sub_un : SubRegIndex<1, 3>;
1818
def sub_32 : SubRegIndex<32>;
1919
def sub_64 : SubRegIndex<64>;
2020
def sub_128 : SubRegIndex<128>;
21-
def subreg_l64 : SubRegIndex<64, 0>;
22-
def subreg_h64 : SubRegIndex<64, 64>;
2321
}
2422

2523

@@ -51,14 +49,6 @@ class FPR<bits<5> num, string n> : PPCReg<n> {
5149
let HWEncoding{4-0} = num;
5250
}
5351

54-
// DPR - One of the 16 128 bit floating-point registers
55-
// It is composed of FPR_even and FPR_odd
56-
class DPR<FPR even, FPR odd, string n> : PPCReg<n> {
57-
let HWEncoding = even.HWEncoding;
58-
let SubRegs = [even, odd];
59-
let SubRegIndices = [subreg_l64, subreg_h64];
60-
}
61-
6252
// QFPR - One of the 32 256-bit floating-point vector registers (used for QPX)
6353
class QFPR<FPR SubReg, string n> : PPCReg<n> {
6454
let HWEncoding = SubReg.HWEncoding;
@@ -126,13 +116,6 @@ foreach Index = 0-31 in {
126116
DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
127117
}
128118

129-
// 128-bit Paired Floating-point registers
130-
foreach Index = 0-15 in {
131-
def D#Index :
132-
DPR<!cast<FPR>("F"#!shl(Index, 1)),
133-
!cast<FPR>("F"#!add(!shl(Index, 1), 1)), "f"#!shl(Index, 1)>;
134-
}
135-
136119
// Floating-point vector subregisters (for VSX)
137120
foreach Index = 0-31 in {
138121
def VF#Index : VF<Index, "vs" # !add(Index, 32)>;
@@ -305,9 +288,6 @@ def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
305288
(sequence "F%u", 31, 14))>;
306289
def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
307290

308-
def D8RC : RegisterClass<"PPC", [f128], 128, (add (sequence "D%u", 0, 6),
309-
(sequence "D%u", 15, 7))>;
310-
311291
def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32], 128,
312292
(add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
313293
V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,

‎lib/Target/PowerPC/README_P9.txt

Lines changed: 0 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -582,79 +582,6 @@ Move to CR from XER Extended (mcrxrx):
582582
- Is there a use for this in LLVM?
583583

584584
Fixed Point Facility:
585-
- Add PC Immediate Shifted: addpcis subpcis
586-
. Thinking to use it on PC relative addressing mode?
587-
588-
- 64-bit Fixed-Point Multiply-Add Low DWord: maddld
589-
. SDAG:
590-
(set i64:$rD, (add (mul $rA, $rB), $rC))
591-
592-
- 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned: maddhd maddhdu
593-
. Use intrinsic:
594-
(set i64:$rD, (int_ppc_maddhd i64:$rA, i64:$rB), i64:$rC))
595-
(set i64:$rD, (int_ppc_maddhdu i64:$rA, i64:$rB), i64:$rC))
596-
597-
- Modulo {Signed/Unsigned}-{Word/DWord}: modsw moduw modsd modud
598-
. Map modulo signed to llvm srem, modulo unsigned to urem because each pair
599-
has same semantics, as follows:
600-
601-
llvm srem:
602-
1. This instruction returns the remainder of a division (where the result is
603-
either zero or has the same sign as the dividend, op1)
604-
2. Undefined behavior:
605-
- <anything> % 0
606-
- Overflow: e.g. -2147483648 % -1
607-
In this case, the remainder doesn’t actually overflow, but this rule
608-
lets srem be implemented using instructions that return both the result
609-
of the division and the remainder.
610-
611-
Modulo Signed:
612-
1. remainder = dividend - (quotient × divisor)
613-
where
614-
0 ≤ remainder < |divisor|, if the dividend ≥ 0
615-
-|divisor| < remainder ≤ 0 , if the dividend < 0
616-
617-
2. Undefined behavior:
618-
- <anything> % 0
619-
- 0x8000_0000 % -1
620-
621-
. SDAG:
622-
(set i32:$rD, (srem i32:$rA, i32:$rB)) // modsw
623-
(set i32:$rD, (urem i32:$rA, i32:$rB)) // moduw
624-
(set i64:$rD, (srem i64:$rA, i64:$rB)) // modsd
625-
(set i64:$rD, (urem i64:$rA, i64:$rB)) // modud
626-
627-
. Note:
628-
The quotient is not supplied as a result in modulo word (32-bit)
629-
instructions
630-
631-
- Deliver A Random Number: darn
632-
. Intrinsic?
633-
(set i64:$rD, (int_ppc_darn i2:$L))
634-
635-
. Thinking for using it on c/c++ rand() implementation
636-
637-
- Extend-Sign Word and Shift Left Immediate: extswsli extswsli.
638-
. SDAG:
639-
(set i64:$rA, shl((sext i32:$rS, i64), i6$SH))
640-
641-
- Set Boolean: setb
642-
. Thinking to use it on:
643-
644-
if (cond)
645-
return true;
646-
return false;
647-
648-
. Need Intrinsic?
649-
(set i64:rD, (int_ppc_setb i3:$BFA))
650-
651-
- DFP Test Significance Immediate [Quad]: dtstsfi dtstsfiq
652-
. Need write inline assembly to test paired floating point register
653-
allocation for dtstsfiq
654-
655-
. Intrinsics:
656-
(set i1:$BF, (int_ppc_dtstsfi i6:$UIM, f64:$FRB))
657-
(set i1:$BF, (int_ppc_dtstsfiq i6:$UIM, f128:$FRBp))
658585

659586
- Copy-Paste Facility: copy copy_first cp_abort paste paste. paste_last
660587
. Use instrinstics:

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