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1 | 1 | source [find interface/cmsis-dap.cfg] |
2 | | -source [find target/lpc17xx.cfg] |
| 2 | + |
| 3 | +# The below contents are is copied from the OpenOCD scripts for the lpc1768 with only *one* change: |
| 4 | +# the "flash bank" line has been commented out so that we can configure the bank manually. |
| 5 | +# I wasn't able to find a way to use the lpc17xx.cfg include file and not have it run this line. |
| 6 | +# Original sources: |
| 7 | +# - https://github.com/openocd-org/openocd/blob/master/tcl/target/lpc17xx.cfg |
| 8 | +# - https://github.com/openocd-org/openocd/blob/master/tcl/target/lpc1xxx.cfg |
| 9 | + |
| 10 | +# SPDX-License-Identifier: GPL-2.0-or-later |
| 11 | + |
| 12 | +# NXP LPC17xx Cortex-M3 with at least 8kB SRAM |
| 13 | +set CHIPNAME lpc17xx |
| 14 | +set CHIPSERIES lpc1700 |
| 15 | +if { ![info exists WORKAREASIZE] } { |
| 16 | + set WORKAREASIZE 0x2000 |
| 17 | +} |
| 18 | + |
| 19 | +# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts |
| 20 | +# |
| 21 | +# !!!!!! |
| 22 | +# |
| 23 | +# This file should not be included directly, rather by the lpc11xx.cfg, |
| 24 | +# lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the |
| 25 | +# appropriate values. |
| 26 | +# |
| 27 | +# !!!!!! |
| 28 | + |
| 29 | +# LPC8xx chips support only SWD transport. |
| 30 | +# LPC11xx chips support only SWD transport. |
| 31 | +# LPC12xx chips support only SWD transport. |
| 32 | +# LPC11Uxx chips support only SWD transports. |
| 33 | +# LPC13xx chips support only SWD transports. |
| 34 | +# LPC17xx chips support both JTAG and SWD transports. |
| 35 | +# LPC40xx chips support both JTAG and SWD transports. |
| 36 | +# Adapt based on what transport is active. |
| 37 | +source [find target/swj-dp.tcl] |
| 38 | + |
| 39 | +if { [info exists CHIPNAME] } { |
| 40 | + set _CHIPNAME $CHIPNAME |
| 41 | +} else { |
| 42 | + error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)." |
| 43 | +} |
| 44 | + |
| 45 | +if { [info exists CHIPSERIES] } { |
| 46 | + # Validate chip series is supported |
| 47 | + if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } { |
| 48 | + error "Unsupported LPC1xxx chip series specified." |
| 49 | + } |
| 50 | + set _CHIPSERIES $CHIPSERIES |
| 51 | +} else { |
| 52 | + error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)." |
| 53 | +} |
| 54 | + |
| 55 | +# After reset, the chip is clocked by an internal RC oscillator. |
| 56 | +# When board-specific code (reset-init handler or device firmware) |
| 57 | +# configures another oscillator and/or PLL0, set CCLK to match; if |
| 58 | +# you don't, then flash erase and write operations may misbehave. |
| 59 | +# (The ROM code doing those updates cares about core clock speed...) |
| 60 | +# CCLK is the core clock frequency in KHz |
| 61 | +if { [info exists CCLK] } { |
| 62 | + # Allow user override |
| 63 | + set _CCLK $CCLK |
| 64 | +} else { |
| 65 | + # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x) |
| 66 | + if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } { |
| 67 | + set _CCLK 12000 |
| 68 | + } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { |
| 69 | + set _CCLK 4000 |
| 70 | + } |
| 71 | +} |
| 72 | + |
| 73 | +if { [info exists CPUTAPID] } { |
| 74 | + # Allow user override |
| 75 | + set _CPUTAPID $CPUTAPID |
| 76 | +} else { |
| 77 | + # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core. |
| 78 | + if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } { |
| 79 | + set _CPUTAPID 0x0bb11477 |
| 80 | + } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { |
| 81 | + if { [using_jtag] } { |
| 82 | + set _CPUTAPID 0x4ba00477 |
| 83 | + } { |
| 84 | + set _CPUTAPID 0x2ba01477 |
| 85 | + } |
| 86 | + } |
| 87 | +} |
| 88 | + |
| 89 | +if { [info exists WORKAREASIZE] } { |
| 90 | + set _WORKAREASIZE $WORKAREASIZE |
| 91 | +} else { |
| 92 | + error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE." |
| 93 | +} |
| 94 | + |
| 95 | +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID |
| 96 | +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu |
| 97 | + |
| 98 | +set _TARGETNAME $_CHIPNAME.cpu |
| 99 | +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap |
| 100 | + |
| 101 | +# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) |
| 102 | +# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) |
| 103 | +# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) |
| 104 | +# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) |
| 105 | +# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) |
| 106 | +# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000) |
| 107 | +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE |
| 108 | + |
| 109 | +# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000) |
| 110 | +# The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000) |
| 111 | +# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000) |
| 112 | +# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000) |
| 113 | +# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000) |
| 114 | +# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000) |
| 115 | +# |
| 116 | +# All are compatible with the "lpc1700" variant of the LPC2000 flash driver |
| 117 | +# (same cmd51 destination boundary alignment, and all three support 256 byte |
| 118 | +# transfers). |
| 119 | +# |
| 120 | +# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] [iap entry] |
| 121 | +set _IAP_ENTRY 0 |
| 122 | +if { [info exists IAP_ENTRY] } { |
| 123 | + set _IAP_ENTRY $IAP_ENTRY |
| 124 | +} |
| 125 | +set _FLASHNAME $_CHIPNAME.flash |
| 126 | +#flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \ |
| 127 | +# lpc1700 $_CCLK calc_checksum $_IAP_ENTRY |
| 128 | + |
| 129 | +if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } { |
| 130 | + # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select |
| 131 | + # "User Flash Mode" where interrupt vectors are _not_ remapped, |
| 132 | + # and reside in flash instead). |
| 133 | + # |
| 134 | + # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description |
| 135 | + # Bit Symbol Value Description |
| 136 | + # 1:0 MAP System memory remap |
| 137 | + # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. |
| 138 | + # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM. |
| 139 | + # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. |
| 140 | + # 31:2 - - Reserved. |
| 141 | + $_TARGETNAME configure -event reset-init { |
| 142 | + mww 0x40048000 0x02 |
| 143 | + } |
| 144 | +} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { |
| 145 | + # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select |
| 146 | + # "User Flash Mode" where interrupt vectors are _not_ remapped, |
| 147 | + # and reside in flash instead). |
| 148 | + # |
| 149 | + # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description |
| 150 | + # Bit Symbol Value Description Reset |
| 151 | + # value |
| 152 | + # 0 MAP Memory map control. 0 |
| 153 | + # 0 Boot mode. A portion of the Boot ROM is mapped to address 0. |
| 154 | + # 1 User mode. The on-chip Flash memory is mapped to address 0. |
| 155 | + # 31:1 - Reserved. The value read from a reserved bit is not defined. NA |
| 156 | + # |
| 157 | + # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user |
| 158 | + $_TARGETNAME configure -event reset-init { |
| 159 | + mww 0x400FC040 0x01 |
| 160 | + } |
| 161 | +} |
| 162 | + |
| 163 | +# Run with *real slow* clock by default since the |
| 164 | +# boot rom could have been playing with the PLL, so |
| 165 | +# we have no idea what clock the target is running at. |
| 166 | +adapter speed 10 |
| 167 | + |
| 168 | +# delays on reset lines |
| 169 | +adapter srst delay 200 |
| 170 | +if {[using_jtag]} { |
| 171 | + jtag_ntrst_delay 200 |
| 172 | +} |
| 173 | + |
| 174 | +# LPC8xx (Cortex-M0+ core) support SYSRESETREQ |
| 175 | +# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ |
| 176 | +# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ |
| 177 | +# LPC40xx (Cortex-M4F core) support SYSRESETREQ |
| 178 | +if {![using_hla]} { |
| 179 | + # if srst is not fitted use SYSRESETREQ to |
| 180 | + # perform a soft reset |
| 181 | + cortex_m reset_config sysresetreq |
| 182 | +} |
| 183 | + |
| 184 | + |
| 185 | +# It seems like there's some sort of issue with the OpenOCD memory auto-probing for this part. |
| 186 | +# When connecting, you often (though not always) get: |
| 187 | +# |
| 188 | +# Debug: 265 9395 lpc2000.c:850 lpc2000_iap_call(): IAP command = 54 (0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000) completed with result = 0737212c |
| 189 | +# Debug: 266 9395 target.c:2143 target_free_working_area_restore(): freed 260 bytes of working area at address 0x10000000 |
| 190 | +# Debug: 267 9395 target.c:1940 print_wa_layout(): 0x10000000-0x10001fff (8192 bytes) |
| 191 | +# Error: 268 9395 lpc2000.c:1513 lpc2000_auto_probe_flash(): BUG: unknown Part ID encountered: 0xaaa0 |
| 192 | +# |
| 193 | +# We can avoid this by manually configuring the flash driver instead of using autoprobing. |
| 194 | +flash bank $_FLASHNAME lpc2000 0x0 0x00080000 0 0 $_TARGETNAME lpc1700 $_CCLK calc_checksum $_IAP_ENTRY |
3 | 195 |
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4 | 196 | # For some reason, the bundled OpenOCD LPC1768 scripts set a _very_ slow default speed that makes programming |
5 | 197 | # take several minutes. Increasing it seems to work OK. |
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