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michaelmaitlandmichaelmaitland
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[RISCV][VLOPT] Add vector indexed loads and stores to getOperandInfo (llvm#119748)
Use `MO.getOperandNo() == 0` instead of `IsMODef` so naming is clear for the store, since the store should treat its operand 0 like that even though it is not a def.The load should treat its operand 0 def in the same way.
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6 files changed

+577
-535
lines changed

6 files changed

+577
-535
lines changed

‎llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -270,6 +270,43 @@ static OperandInfo getOperandInfo(const MachineOperand &MO,
270270
case RISCV::VSSE64_V:
271271
return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(6, MI), 6);
272272

273+
// Vector Indexed Instructions
274+
// vs(o|u)xei<eew>.v
275+
// Dest/Data (operand 0) EEW=SEW, EMUL=LMUL. Source EEW=<eew> and
276+
// EMUL=(EEW/SEW)*LMUL.
277+
case RISCV::VLUXEI8_V:
278+
case RISCV::VLOXEI8_V:
279+
case RISCV::VSUXEI8_V:
280+
case RISCV::VSOXEI8_V: {
281+
if (MO.getOperandNo() == 0)
282+
return OperandInfo(MIVLMul, MILog2SEW);
283+
return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(3, MI), 3);
284+
}
285+
case RISCV::VLUXEI16_V:
286+
case RISCV::VLOXEI16_V:
287+
case RISCV::VSUXEI16_V:
288+
case RISCV::VSOXEI16_V: {
289+
if (MO.getOperandNo() == 0)
290+
return OperandInfo(MIVLMul, MILog2SEW);
291+
return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(4, MI), 4);
292+
}
293+
case RISCV::VLUXEI32_V:
294+
case RISCV::VLOXEI32_V:
295+
case RISCV::VSUXEI32_V:
296+
case RISCV::VSOXEI32_V: {
297+
if (MO.getOperandNo() == 0)
298+
return OperandInfo(MIVLMul, MILog2SEW);
299+
return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(5, MI), 5);
300+
}
301+
case RISCV::VLUXEI64_V:
302+
case RISCV::VLOXEI64_V:
303+
case RISCV::VSUXEI64_V:
304+
case RISCV::VSOXEI64_V: {
305+
if (MO.getOperandNo() == 0)
306+
return OperandInfo(MIVLMul, MILog2SEW);
307+
return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(6, MI), 6);
308+
}
309+
273310
// Vector Integer Arithmetic Instructions
274311
// Vector Single-Width Integer Add and Subtract
275312
case RISCV::VADD_VI:

‎llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,10 @@ declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
1010
define <vscale x 4 x i32> @test_vloxei(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
1111
; CHECK-LABEL: test_vloxei:
1212
; CHECK: # %bb.0: # %entry
13-
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma
13+
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
1414
; CHECK-NEXT: vzext.vf8 v12, v8
1515
; CHECK-NEXT: vsll.vi v12, v12, 4
16-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
16+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1717
; CHECK-NEXT: vloxei64.v v8, (a0), v12
1818
; CHECK-NEXT: ret
1919
entry:
@@ -30,10 +30,10 @@ entry:
3030
define <vscale x 4 x i32> @test_vloxei2(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
3131
; CHECK-LABEL: test_vloxei2:
3232
; CHECK: # %bb.0: # %entry
33-
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma
33+
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
3434
; CHECK-NEXT: vzext.vf8 v12, v8
3535
; CHECK-NEXT: vsll.vi v12, v12, 14
36-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
36+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
3737
; CHECK-NEXT: vloxei64.v v8, (a0), v12
3838
; CHECK-NEXT: ret
3939
entry:
@@ -50,10 +50,10 @@ entry:
5050
define <vscale x 4 x i32> @test_vloxei3(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
5151
; CHECK-LABEL: test_vloxei3:
5252
; CHECK: # %bb.0: # %entry
53-
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma
53+
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
5454
; CHECK-NEXT: vzext.vf8 v12, v8
5555
; CHECK-NEXT: vsll.vi v12, v12, 26
56-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
56+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
5757
; CHECK-NEXT: vloxei64.v v8, (a0), v12
5858
; CHECK-NEXT: ret
5959
entry:
@@ -74,9 +74,8 @@ define <vscale x 4 x i32> @test_vloxei4(ptr %ptr, <vscale x 4 x i8> %offset, <vs
7474
; CHECK: # %bb.0: # %entry
7575
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
7676
; CHECK-NEXT: vzext.vf8 v12, v8, v0.t
77-
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma
7877
; CHECK-NEXT: vsll.vi v12, v12, 4
79-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
78+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
8079
; CHECK-NEXT: vloxei64.v v8, (a0), v12
8180
; CHECK-NEXT: ret
8281
entry:
@@ -100,10 +99,10 @@ declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(
10099
define <vscale x 4 x i32> @test_vloxei5(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
101100
; CHECK-LABEL: test_vloxei5:
102101
; CHECK: # %bb.0: # %entry
103-
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
102+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
104103
; CHECK-NEXT: vzext.vf2 v9, v8
105104
; CHECK-NEXT: vsll.vi v10, v9, 12
106-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
105+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
107106
; CHECK-NEXT: vloxei16.v v8, (a0), v10
108107
; CHECK-NEXT: ret
109108
entry:
@@ -121,12 +120,12 @@ define <vscale x 4 x i32> @test_vloxei6(ptr %ptr, <vscale x 4 x i7> %offset, i64
121120
; CHECK-LABEL: test_vloxei6:
122121
; CHECK: # %bb.0: # %entry
123122
; CHECK-NEXT: li a2, 127
124-
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
123+
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
125124
; CHECK-NEXT: vand.vx v8, v8, a2
126125
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
127126
; CHECK-NEXT: vzext.vf8 v12, v8
128127
; CHECK-NEXT: vsll.vi v12, v12, 4
129-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
128+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
130129
; CHECK-NEXT: vloxei64.v v8, (a0), v12
131130
; CHECK-NEXT: ret
132131
entry:
@@ -146,8 +145,9 @@ define <vscale x 4 x i32> @test_vloxei7(ptr %ptr, <vscale x 4 x i1> %offset, i64
146145
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma
147146
; CHECK-NEXT: vmv.v.i v8, 0
148147
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
148+
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
149149
; CHECK-NEXT: vsll.vi v12, v8, 2
150-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
150+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
151151
; CHECK-NEXT: vloxei64.v v8, (a0), v12
152152
; CHECK-NEXT: ret
153153
entry:
@@ -172,10 +172,10 @@ declare <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i64(
172172
define <vscale x 4 x i32> @test_vloxei_mask(ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i64 %vl) {
173173
; CHECK-LABEL: test_vloxei_mask:
174174
; CHECK: # %bb.0: # %entry
175-
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma
175+
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
176176
; CHECK-NEXT: vzext.vf8 v12, v8
177177
; CHECK-NEXT: vsll.vi v12, v12, 4
178-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
178+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
179179
; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t
180180
; CHECK-NEXT: ret
181181
entry:
@@ -199,10 +199,10 @@ declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64(
199199
define <vscale x 4 x i32> @test_vluxei(ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
200200
; CHECK-LABEL: test_vluxei:
201201
; CHECK: # %bb.0: # %entry
202-
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma
202+
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
203203
; CHECK-NEXT: vzext.vf8 v12, v8
204204
; CHECK-NEXT: vsll.vi v12, v12, 4
205-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
205+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
206206
; CHECK-NEXT: vluxei64.v v8, (a0), v12
207207
; CHECK-NEXT: ret
208208
entry:
@@ -227,10 +227,10 @@ declare <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i64(
227227
define <vscale x 4 x i32> @test_vluxei_mask(ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i64 %vl) {
228228
; CHECK-LABEL: test_vluxei_mask:
229229
; CHECK: # %bb.0: # %entry
230-
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma
230+
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
231231
; CHECK-NEXT: vzext.vf8 v12, v8
232232
; CHECK-NEXT: vsll.vi v12, v12, 4
233-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
233+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
234234
; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t
235235
; CHECK-NEXT: ret
236236
entry:
@@ -254,10 +254,10 @@ declare void @llvm.riscv.vsoxei.nxv4i32.nxv4i64(
254254
define void @test_vsoxei(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
255255
; CHECK-LABEL: test_vsoxei:
256256
; CHECK: # %bb.0: # %entry
257-
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma
257+
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
258258
; CHECK-NEXT: vzext.vf8 v12, v10
259259
; CHECK-NEXT: vsll.vi v12, v12, 4
260-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
260+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
261261
; CHECK-NEXT: vsoxei64.v v8, (a0), v12
262262
; CHECK-NEXT: ret
263263
entry:
@@ -281,10 +281,10 @@ declare void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i64(
281281
define void @test_vsoxei_mask(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i64 %vl) {
282282
; CHECK-LABEL: test_vsoxei_mask:
283283
; CHECK: # %bb.0: # %entry
284-
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma
284+
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
285285
; CHECK-NEXT: vzext.vf8 v12, v10
286286
; CHECK-NEXT: vsll.vi v12, v12, 4
287-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
287+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
288288
; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
289289
; CHECK-NEXT: ret
290290
entry:
@@ -308,10 +308,10 @@ declare void @llvm.riscv.vsuxei.nxv4i32.nxv4i64(
308308
define void @test_vsuxei(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i8> %offset, i64 %vl) {
309309
; CHECK-LABEL: test_vsuxei:
310310
; CHECK: # %bb.0: # %entry
311-
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma
311+
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
312312
; CHECK-NEXT: vzext.vf8 v12, v10
313313
; CHECK-NEXT: vsll.vi v12, v12, 4
314-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
314+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
315315
; CHECK-NEXT: vsuxei64.v v8, (a0), v12
316316
; CHECK-NEXT: ret
317317
entry:
@@ -335,10 +335,10 @@ declare void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i64(
335335
define void @test_vsuxei_mask(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i8> %offset, <vscale x 4 x i1> %m, i64 %vl) {
336336
; CHECK-LABEL: test_vsuxei_mask:
337337
; CHECK: # %bb.0: # %entry
338-
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma
338+
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
339339
; CHECK-NEXT: vzext.vf8 v12, v10
340340
; CHECK-NEXT: vsll.vi v12, v12, 4
341-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
341+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
342342
; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t
343343
; CHECK-NEXT: ret
344344
entry:

‎llvm/test/CodeGen/RISCV/rvv/pr63459.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,10 @@ define void @snork(ptr %arg, <vscale x 2 x i64> %arg1) {
55
; CHECK-LABEL: snork:
66
; CHECK: # %bb.0: # %bb
77
; CHECK-NEXT: csrr a1, vlenb
8-
; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, ma
8+
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
99
; CHECK-NEXT: vmul.vx v8, v8, a1
1010
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
1111
; CHECK-NEXT: vmv.v.i v10, 1
12-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
1312
; CHECK-NEXT: vsoxei64.v v10, (a0), v8
1413
; CHECK-NEXT: ret
1514
bb:

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir

Lines changed: 102 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -573,6 +573,108 @@ body: |
573573
PseudoVSSE8_V_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */
574574
...
575575
---
576+
name: vsuxeiN_v_data
577+
body: |
578+
bb.0:
579+
; CHECK-LABEL: name: vsuxeiN_v_data
580+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
581+
; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */
582+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
583+
PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */
584+
...
585+
---
586+
name: vsuxeiN_v_data_incompatible_eew
587+
body: |
588+
bb.0:
589+
; CHECK-LABEL: name: vsuxeiN_v_data_incompatible_eew
590+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
591+
; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */
592+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
593+
PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */
594+
...
595+
---
596+
name: vsuxeiN_v_data_incompatible_emul
597+
body: |
598+
bb.0:
599+
; CHECK-LABEL: name: vsuxeiN_v_data_incompatible_emul
600+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
601+
; CHECK-NEXT: PseudoVSUXEI8_V_MF2_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */
602+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
603+
PseudoVSUXEI8_V_MF2_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */
604+
...
605+
---
606+
name: vsuxeiN_v_idx
607+
body: |
608+
bb.0:
609+
; CHECK-LABEL: name: vsuxeiN_v_idx
610+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
611+
; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */
612+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
613+
PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */
614+
...
615+
---
616+
name: vsuxeiN_v_idx_incompatible_eew
617+
body: |
618+
bb.0:
619+
; CHECK-LABEL: name: vsuxeiN_v_idx_incompatible_eew
620+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
621+
; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
622+
; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */
623+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
624+
%y:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
625+
PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */
626+
...
627+
---
628+
name: vsuxeiN_v_idx_incompatible_emul
629+
body: |
630+
bb.0:
631+
; CHECK-LABEL: name: vsuxeiN_v_idx_incompatible_emul
632+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
633+
; CHECK-NEXT: PseudoVSUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */
634+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
635+
PseudoVSUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */
636+
...
637+
---
638+
name: vluxeiN_v_data
639+
body: |
640+
bb.0:
641+
; CHECK-LABEL: name: vluxeiN_v_data
642+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
643+
; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
644+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
645+
%y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
646+
...
647+
---
648+
name: vluxeiN_v_incompatible_eew
649+
body: |
650+
bb.0:
651+
; CHECK-LABEL: name: vluxeiN_v_incompatible_eew
652+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
653+
; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
654+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
655+
%y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
656+
...
657+
---
658+
name: vluxeiN_v_data_incompatible_emul
659+
body: |
660+
bb.0:
661+
; CHECK-LABEL: name: vluxeiN_v_data_incompatible_emul
662+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
663+
; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
664+
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
665+
%y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
666+
...
667+
---
668+
name: vluxeiN_v_idx
669+
body: |
670+
bb.0:
671+
; CHECK-LABEL: name: vluxeiN_v_idx
672+
; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
673+
; CHECK-NEXT: early-clobber %y:vr = PseudoVLUXEI8_V_MF2_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */
674+
%x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
675+
%y:vr = PseudoVLUXEI8_V_MF2_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0
676+
...
677+
---
576678
name: vmop_mm
577679
body: |
578680
bb.0:

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