[RISCV][VLOPT] Add vector indexed loads and stores to getOperandInfo

[michaelmaitland]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Michael Maitland (michaelmaitland)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/119748.diff

2 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp (+28)
• (modified) llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir (+30)

diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 1d5684d6038ea9..dc17ee061e48fd 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -270,6 +270,34 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
   case RISCV::VSSE64_V:
     return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(6, MI), 6);
 
+  // Vector Indexed Instructions
+  // vs(o|u)xei<eew>.v
+  // Dest EEW=SEW, EMUL=LMUL. Source EEW=<eew> and EMUL=(EEW/SEW)*LMUL
+  case RISCV::VSUXEI8_V:
+  case RISCV::VSOXEI8_V: {
+    if (IsMODef)
+      return OperandInfo(MIVLMul, MILog2SEW);
+    return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(3, MI), 3);
+  }
+  case RISCV::VSUXEI16_V:
+  case RISCV::VSOXEI16_V: {
+    if (IsMODef)
+      return OperandInfo(MIVLMul, MILog2SEW);
+    return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(4, MI), 4);
+  }
+  case RISCV::VSUXEI32_V:
+  case RISCV::VSOXEI32_V: {
+    if (IsMODef)
+      return OperandInfo(MIVLMul, MILog2SEW);
+    return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(5, MI), 5);
+  }
+  case RISCV::VSUXEI64_V:
+  case RISCV::VSOXEI64_V: {
+    if (IsMODef)
+      return OperandInfo(MIVLMul, MILog2SEW);
+    return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(6, MI), 6);
+  }
+
   // Vector Integer Arithmetic Instructions
   // Vector Single-Width Integer Add and Subtract
   case RISCV::VADD_VI:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index f1e7bb446482e1..c68dda161b7cb4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -543,6 +543,36 @@ body: |
     PseudoVSSE8_V_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */
 ...
 ---
+name: vsuxeiN_v
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: vsuxeiN_v
+    ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+    ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */
+    %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+    PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */
+...
+---
+name: vsuxeiN_v_incompatible_eew
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: vsuxeiN_v_incompatible_eew
+    ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+    ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */
+    %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
+    PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */
+...
+---
+name: vsuxeiN_v_incompatible_emul
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: vsuxeiN_v_incompatible_emul
+    ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+    ; CHECK-NEXT: PseudoVSUXEI8_V_MF2_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */
+    %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+    PseudoVSUXEI8_V_MF2_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */
+...
+---
 name: vmop_mm
 body: |
   bb.0:

[topperc]

IsMODef isn't named well for a store. It's not a def, but it happens to be operand 0 so it works.

[topperc]

Where does this requirement come from?

[michaelmaitland]

It was because I was missing a rebase.

[topperc]

It's no longer incompatible. It's being optimized.

[michaelmaitland]

changed.

[topperc]

What is the VADD for? It has the same LMUL but different EEW than the VLUX dest.

[michaelmaitland]

removed.

[topperc]

I think this instruction is malformed. One of the M1 needs to be MF2 to match the VADD.

[topperc]

I think the index is first so it should be PseudoVLUXEI8_V_MF2_M1

[michaelmaitland]

addressed.

[topperc]

LGTM

[lukel97]

LGTM

[michaelmaitland]

I had to update some test checks after rebase. Would appreciate another look through. Sorry about that.

[topperc]

LGTM