Merge pull request #31 from arjanmels/feature-mutex-trait

Added Mutexes implemented in xtensa-lx6 to prelude & started using in timers example

Author: MabezDev

.gitignore

@@ -2,4 +2,5 @@
 procmacros/target
 **/*.rs.bk
 Cargo.lock
-.vscode/.cortex-debug*
+.vscode/.cortex-debug*
+core

Cargo.toml

@@ -32,12 +32,11 @@ rt = ["esp32/rt", "xtensa-lx6-rt"]
 [dependencies]
 esp32-hal-proc-macros = { path = "procmacros" }
 
-xtensa-lx6-rt = { version = "0.2.0", optional = true }
-xtensa-lx6 = "0.1.0"
-esp32 = { version = "0.5.0", default-features = false }
+xtensa-lx6-rt = { version = "0.3.0", optional = true }
+xtensa-lx6 = "0.2.0"
+esp32 = "0.5.0"
 bare-metal = "0.2"
 nb = "0.1.2"
-spin = "0.5.2"
 embedded-hal = { version = "0.2.3", features = ["unproven"] }
 linked_list_allocator = { version = "0.8.4", optional = true, default-features = false, features = ["alloc_ref"] }
 void = { version = "1.0.2", default-features = false }

core

@@ -5,9 +5,9 @@ extern crate esp32_hal as hal;
 extern crate panic_halt;
 extern crate xtensa_lx6_rt;
 
+use esp32_hal::target;
 use hal::prelude::*;
-use hal::target;
-use xtensa_lx6::get_cycle_count;
+use xtensa_lx6::timer::get_cycle_count;
 
 /// The default clock source is the onboard crystal
 /// In most cases 40mhz (but can be as low as 2mhz depending on the board)

examples/blinky.rs

@@ -16,79 +16,62 @@ use esp32_hal::serial::{config::Config, NoRx, NoTx, Serial};
 use esp32_hal::target;
 use esp32_hal::Core::PRO;
 
-static TX: spin::Mutex<Option<esp32_hal::serial::Tx<target::UART0>>> = spin::Mutex::new(None);
+// !!! Cannot use CriticalSectionSpinLockMutex here, because an NMI is fires from within a locked
+// section which leads to a deadlock in the NMI interrupt handler. This is not a problem in this
+// case as this is a single threaded example. !!!
+static TX: xtensa_lx6::mutex::CriticalSectionMutex<Option<esp32_hal::serial::Tx<esp32::UART0>>> =
+    xtensa_lx6::mutex::CriticalSectionMutex::new(None);
+
+fn locked_print(str: &str) {
+    (&TX).lock(|tx| {
+        let tx = tx.as_mut().unwrap();
+
+        writeln!(
+            tx,
+            "    {}, Level: {}",
+            str,
+            xtensa_lx6::interrupt::get_level()
+        )
+        .unwrap();
+    });
+}
 
 #[interrupt]
 fn FROM_CPU_INTR0() {
-    writeln!(
-        TX.lock().as_mut().unwrap(),
-        "  FROM_CPU_INTR0, level: {}",
-        xtensa_lx6::interrupt::get_level()
-    )
-    .unwrap();
+    locked_print("FROM_CPU_INTR0");
     clear_software_interrupt(Interrupt::FROM_CPU_INTR0).unwrap();
 }
 
 #[interrupt]
 fn FROM_CPU_INTR1() {
-    writeln!(
-        TX.lock().as_mut().unwrap(),
-        "  Start FROM_CPU_INTR1, level: {}",
-        xtensa_lx6::interrupt::get_level()
-    )
-    .unwrap();
+    locked_print("Start FROM_CPU_INTR1");
     interrupt::set_software_interrupt(Interrupt::FROM_CPU_INTR0).unwrap();
     interrupt::set_software_interrupt(Interrupt::FROM_CPU_INTR2).unwrap();
-    writeln!(
-        TX.lock().as_mut().unwrap(),
-        "  End FROM_CPU_INTR1, level: {}",
-        xtensa_lx6::interrupt::get_level()
-    )
-    .unwrap();
+    locked_print("End FROM_CPU_INTR1");
     clear_software_interrupt(Interrupt::FROM_CPU_INTR1).unwrap();
 }
 
 #[interrupt]
 fn FROM_CPU_INTR2() {
-    writeln!(
-        TX.lock().as_mut().unwrap(),
-        "  FROM_CPU_INTR2, level: {}",
-        xtensa_lx6::interrupt::get_level()
-    )
-    .unwrap();
+    locked_print("FROM_CPU_INTR2");
     clear_software_interrupt(Interrupt::FROM_CPU_INTR2).unwrap();
 }
 
 #[interrupt]
 fn FROM_CPU_INTR3() {
-    writeln!(
-        TX.lock().as_mut().unwrap(),
-        "  FROM_CPU_INTR3, level: {}",
-        xtensa_lx6::interrupt::get_level()
-    )
-    .unwrap();
+    locked_print("FROM_CPU_INTR3");
     clear_software_interrupt(Interrupt::FROM_CPU_INTR3).unwrap();
 }
 
 #[interrupt(INTERNAL_SOFTWARE_LEVEL_3_INTR)]
 fn software_level_3() {
-    writeln!(
-        TX.lock().as_mut().unwrap(),
-        "  INTERNAL_SOFTWARE_LEVEL_3_INTR, level: {}",
-        xtensa_lx6::interrupt::get_level()
-    )
-    .unwrap();
+    locked_print("INTERNAL_SOFTWARE_LEVEL_3_INTR");
     clear_software_interrupt(Interrupt::FROM_CPU_INTR3).unwrap();
 }
 
 #[interrupt(INTERNAL_SOFTWARE_LEVEL_1_INTR)]
 fn random_name() {
-    writeln!(
-        TX.lock().as_mut().unwrap(),
-        "  INTERNAL_SOFTWARE_LEVEL_1_INTR, level: {}",
-        xtensa_lx6::interrupt::get_level()
-    )
-    .unwrap();
+    locked_print("INTERNAL_SOFTWARE_LEVEL_1_INTR");
     clear_software_interrupt(Interrupt::FROM_CPU_INTR3).unwrap();
 }
 
@@ -98,13 +81,10 @@ fn other_exception(
     cause: xtensa_lx6_rt::exception::ExceptionCause,
     frame: xtensa_lx6_rt::exception::Context,
 ) {
-    writeln!(
-        TX.lock().as_mut().unwrap(),
-        "Exception {:?}, {:08x?}",
-        cause,
-        frame
-    )
-    .unwrap();
+    (&TX).lock(|tx| {
+        let tx = tx.as_mut().unwrap();
+        writeln!(tx, "Exception {:?}, {:08x?}", cause, frame).unwrap();
+    });
     loop {}
 }
 
@@ -156,7 +136,7 @@ fn main() -> ! {
     writeln!(uart0, "\n\nReboot!\n",).unwrap();
 
     let (tx, _) = uart0.split();
-    *TX.lock() = Some(tx);
+    (&TX).lock(|tx_locked| *tx_locked = Some(tx));
 
     interrupt::enable_with_priority(PRO, Interrupt::FROM_CPU_INTR0, InterruptLevel(2)).unwrap();
     interrupt::enable_with_priority(PRO, Interrupt::FROM_CPU_INTR1, InterruptLevel(4)).unwrap();
@@ -167,32 +147,40 @@ fn main() -> ! {
 
     // Trigger various software interrupts, because done in an interrupt free section will
     // actually trigger at the end in order of priority
-    interrupt::free(|_| {
-        writeln!(TX.lock().as_mut().unwrap(), "Start Trigger Interrupts",).unwrap();
+    (&TX).lock(|tx| {
+        let tx = tx.as_mut().unwrap();
+
+        writeln!(tx, "Start Trigger Interrupts",).unwrap();
         interrupt::set_software_interrupt(Interrupt::FROM_CPU_INTR0).unwrap();
         interrupt::set_software_interrupt(Interrupt::FROM_CPU_INTR1).unwrap();
         interrupt::set_software_interrupt(Interrupt::FROM_CPU_INTR2).unwrap();
         // this one will trigger immediately as level 7 is Non-Maskable Intterupt (NMI)
         interrupt::set_software_interrupt(Interrupt::FROM_CPU_INTR3).unwrap();
         interrupt::set_software_interrupt(Interrupt::INTERNAL_SOFTWARE_LEVEL_1_INTR).unwrap();
         interrupt::set_software_interrupt(Interrupt::INTERNAL_SOFTWARE_LEVEL_3_INTR).unwrap();
-        writeln!(TX.lock().as_mut().unwrap(), "End Trigger Interrupts",).unwrap();
+        writeln!(tx, "End Trigger Interrupts",).unwrap();
     });
 
     // Trigger outside of interrupt free section, triggers immediately
-    writeln!(TX.lock().as_mut().unwrap(), "Start Trigger Interrupt",).unwrap();
+    (&TX).lock(|tx| {
+        let tx = tx.as_mut().unwrap();
+        writeln!(tx, "Start Trigger Interrupt",).unwrap();
+    });
     interrupt::set_software_interrupt(Interrupt::FROM_CPU_INTR0).unwrap();
     interrupt::set_software_interrupt(Interrupt::FROM_CPU_INTR1).unwrap();
     interrupt::set_software_interrupt(Interrupt::FROM_CPU_INTR2).unwrap();
     // this one will trigger immediately as level 7 is Non-Maskable Intterupt (NMI)
     interrupt::set_software_interrupt(Interrupt::FROM_CPU_INTR3).unwrap();
     interrupt::set_software_interrupt(Interrupt::INTERNAL_SOFTWARE_LEVEL_1_INTR).unwrap();
     interrupt::set_software_interrupt(Interrupt::INTERNAL_SOFTWARE_LEVEL_3_INTR).unwrap();
-    writeln!(TX.lock().as_mut().unwrap(), "End Trigger Interrupt",).unwrap();
 
-    // Trigger a LoadStoreError due to unaligned access in the IRAM
+    (&TX).lock(|tx| {
+        let tx = tx.as_mut().unwrap();
+        writeln!(tx, "End Trigger Interrupt",).unwrap();
+        writeln!(tx, "\nTrigger exception:",).unwrap();
+    });
 
-    writeln!(TX.lock().as_mut().unwrap(), "\nTrigger exception:",).unwrap();
+    // Trigger a LoadStoreError due to unaligned access in the IRAM
 
     #[link_section = ".rwtext"]
     static mut IRAM: [u8; 12] = [0; 12];
@@ -203,8 +191,10 @@ fn main() -> ! {
 
     loop {
         sleep(1.s());
-        interrupt::free(|_| {
-            writeln!(TX.lock().as_mut().unwrap(), "Wait for watchdog reset").unwrap()
+        (&TX).lock(|tx| {
+            let tx = tx.as_mut().unwrap();
+
+            writeln!(tx, "Wait for watchdog reset").unwrap()
         });
     }
 }

examples/exception.rs

@@ -12,12 +12,13 @@ use esp32_hal::dprintln;
 use esp32_hal::serial::{config::Config, NoRx, NoTx, Serial};
 use esp32_hal::target;
 
-use xtensa_lx6::{get_cycle_count, get_stack_pointer};
+use xtensa_lx6::{get_stack_pointer, timer::get_cycle_count};
 
 const BLINK_HZ: Hertz = Hertz(1);
 
 static GLOBAL_COUNT: core::sync::atomic::AtomicU32 = core::sync::atomic::AtomicU32::new(0);
-static TX: spin::Mutex<Option<esp32_hal::serial::Tx<target::UART0>>> = spin::Mutex::new(None);
+static TX: CriticalSectionSpinLockMutex<Option<esp32_hal::serial::Tx<esp32::UART0>>> =
+    CriticalSectionSpinLockMutex::new(None);
 
 #[no_mangle]
 fn main() -> ! {
@@ -100,14 +101,12 @@ fn main() -> ! {
     // panic!("panic test");
 
     let (tx, _) = uart0.split();
-    *TX.lock() = Some(tx);
+    (&TX).lock(|locked_tx| *locked_tx = Some(tx));
 
     let _lock = clock_control_config.lock_cpu_frequency();
 
     // start core 1 (APP_CPU)
-    clock_control_config
-        .start_core(esp32_hal::Core::APP, cpu1_start)
-        .unwrap();
+    clock_control_config.start_app_core(cpu1_start).unwrap();
 
     // main loop, which in turn lock and unlocks apb and cpu locks
     let mut x: u32 = 0;
@@ -156,12 +155,14 @@ fn cpu1_start() -> ! {
     let mut x: u32 = 0;
     let mut prev_ccount = 0;
 
-    writeln!(
-        TX.lock().as_mut().unwrap(),
-        "Stack Pointer Core 1: {:08x?}",
-        get_stack_pointer()
-    )
-    .unwrap();
+    (&TX).lock(|tx| {
+        writeln!(
+            tx.as_mut().unwrap(),
+            "Stack Pointer Core 1: {:08x?}",
+            get_stack_pointer()
+        )
+        .unwrap()
+    });
 
     loop {
         let cycles = ClockControlConfig {}.cpu_frequency() / BLINK_HZ;
@@ -182,8 +183,9 @@ fn print_info(loop_count: u32, spin_loop_count: u32, prev_ccount: &mut u32) {
 
     let total = GLOBAL_COUNT.fetch_add(ccount_diff, core::sync::atomic::Ordering::Relaxed);
 
-    writeln!(
-        TX.lock().as_mut().unwrap(),
+    (&TX).lock(|tx| {
+
+    writeln!(tx.as_mut().unwrap(),
         "Core: {:?}, Loop: {}, Spin loops:{}, cycles: {}, cycles since previous {}, Total cycles: {}",
         esp32_hal::get_core(),
         loop_count,
@@ -193,6 +195,7 @@ fn print_info(loop_count: u32, spin_loop_count: u32, prev_ccount: &mut u32) {
         total
     )
     .unwrap();
+    });
 
     *prev_ccount = ccount;
 }

examples/multicore.rs

@@ -118,7 +118,7 @@ fn main() -> ! {
 
                 x = x.wrapping_add(1);
 
-                let ccount = xtensa_lx6::get_cycle_count();
+                let ccount = xtensa_lx6::timer::get_cycle_count();
                 let ccount_diff = ccount.wrapping_sub(prev_ccount);
 
                 writeln!(