Remove genx_faddr intrinsic handlers from IGC

Remove dead code related to genx_faddr intrinsic as it is not generated since 2021

Author: fveselov

IGC/VectorCompiler/lib/GenXCodeGen/GenXBaling.cpp

@@ -213,8 +213,6 @@ void GenXBaling::processInst(Instruction *Inst)
     processWrPredPredRegion(Inst);
   else if (IntrinID == GenXIntrinsic::genx_sat || GenXIntrinsic::isIntegerSat(IntrinID))
     processSat(Inst);
-  else if (IntrinID == GenXIntrinsic::genx_faddr)
-    processFuncPointer(Inst);
   else if (GenXIntrinsic::isReadWritePredefReg(IntrinID))
     processRdWrPredefReg(Inst);
   else if (GenXIntrinsic::isRdRegion(IntrinID))
@@ -1013,29 +1011,6 @@ void GenXBaling::processInlineAsm(Instruction *Inst) {
   setBaleInfo(Inst, BI);
 }
 
-/***********************************************************************
- * processFuncPointer : process genx.faddr which is used in <=1 WrRegions
- *                      and is baled into it.
- */
-void GenXBaling::processFuncPointer(Instruction *Inst) {
-  auto *CI = dyn_cast<CallInst>(Inst);
-  IGC_ASSERT_MESSAGE(CI, "genx.faddr expected");
-  IGC_ASSERT_MESSAGE(GenXIntrinsic::getGenXIntrinsicID(CI) == GenXIntrinsic::genx_faddr,
-    "genx.faddr expected");
-  IGC_ASSERT(Inst->hasOneUse());
-  auto *NextUser = Inst->user_back();
-  if (isa<BitCastInst>(NextUser)) {
-    // bitcasts <N x i64> -> <2*N x i32> may appear after i64 emulation
-    IGC_ASSERT(NextUser->hasOneUse());
-    IGC_ASSERT(NextUser->getType()->getScalarType()->isIntegerTy(32));
-    NextUser = NextUser->user_back();
-  }
-  IGC_ASSERT(NextUser->use_empty() || GenXIntrinsic::isWrRegion(NextUser));
-
-  BaleInfo BI(BaleInfo::FADDR);
-  setBaleInfo(Inst, BI);
-}
-
 void GenXBaling::processRdWrPredefReg(Instruction *Inst) {
   auto *CI = dyn_cast<CallInst>(Inst);
   IGC_ASSERT_MESSAGE((CI && GenXIntrinsic::isReadWritePredefReg(Inst)),
@@ -2717,7 +2692,6 @@ const char *BaleInfo::getTypeString() const
     case BaleInfo::CMPDST: return "cmpdst";
     case BaleInfo::GSTORE: return "g_store";
     case BaleInfo::SHUFFLEPRED: return "shufflepred";
-    case BaleInfo::FADDR: return "faddr";
     default: return "???";
   }
 }

IGC/VectorCompiler/lib/GenXCodeGen/GenXBaling.h

@@ -243,7 +243,7 @@ struct BaleInfo {
   // Type is how this instruction relates to its bale, whether it is a
   // rdregion, wrregion, modifier, or main instruction.
   enum { MAININST, WRREGION, SATURATE, NOTMOD, NEGMOD, ABSMOD,
-      RDREGION, ADDRADD, ADDROR, FADDR, RDPREDREGION, ALLANY, NOTP, ZEXT, SEXT,
+      RDREGION, ADDRADD, ADDROR, RDPREDREGION, ALLANY, NOTP, ZEXT, SEXT,
       SHUFFLEPRED, WRPREDREGION, WRPREDPREDREGION, CMPDST, GSTORE, REGINTR };
   uint16_t Type;
   uint16_t Bits; // bitmap of which operands are baled in
@@ -464,7 +464,6 @@ class GenXBaling {
   void processRdPredRegion(Instruction *Inst);
   void processInlineAsm(Instruction *Inst);
   void processExtractValue(ExtractValueInst *EV);
-  void processFuncPointer(Instruction *Inst);
   void processRdWrPredefReg(Instruction *Inst);
   void processMainInst(Instruction *Inst, int IntrinID);
   bool processSelectToPredicate(SelectInst *SI);

IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp

@@ -598,7 +598,6 @@ class GenXKernelBuilder {
                       unsigned Mod, const DstOpndDesc &DstDesc);
   void buildInputs(Function *F, bool NeedRetIP);
 
-  void buildFunctionAddr(Instruction *Inst, const DstOpndDesc &DstDesc);
   void buildLoneWrRegion(const DstOpndDesc &Desc);
   void buildLoneWrPredRegion(Instruction *Inst, genx::BaleInfo BI);
   void buildLoneOperand(Instruction *Inst, genx::BaleInfo BI, unsigned Mod,
@@ -1660,10 +1659,6 @@ bool GenXKernelBuilder::buildInstruction(Instruction *Inst) {
     Inst = cast<Instruction>(DstDesc.WrRegion->getOperand(OperandNum));
     BI = Baling->getBaleInfo(Inst);
   }
-  if (BI.Type == BaleInfo::FADDR) {
-    buildFunctionAddr(Inst, DstDesc);
-    return false;
-  }
   unsigned Mod = 0;
   if (BI.Type == BaleInfo::SATURATE) {
     // Inst is a fp saturate. See if it bales in the instruction that
@@ -2710,18 +2705,6 @@ void GenXKernelBuilder::buildNoopCast(CastInst *CI, genx::BaleInfo BI,
                           0, false));
 }
 
-void GenXKernelBuilder::buildFunctionAddr(Instruction *Inst,
-                                          const DstOpndDesc &DstDesc) {
-  auto *CI = dyn_cast<CallInst>(Inst);
-  IGC_ASSERT(CI);
-  IGC_ASSERT_MESSAGE(GenXIntrinsic::getGenXIntrinsicID(CI) == GenXIntrinsic::genx_faddr,
-    "genx.faddr expected in a FADDR bale");
-  auto *Dst = createDestination(Inst, DONTCARESIGNED, MODIFIER_NONE, DstDesc);
-  IGC_ASSERT(Dst);
-  auto *F = cast<Function>(Inst->getOperand(0));
-  CISA_CALL(Kernel->AppendVISACFSymbolInst(F->getName().str(), Dst));
-}
-
 /***********************************************************************
  * buildLoneWrRegion : build a lone wrregion
  */

IGC/VectorCompiler/lib/GenXCodeGen/GenXEmulate.cpp

@@ -76,9 +76,6 @@ static cl::opt<bool> OptStricterOword(
 static cl::opt<bool> OptStricterAlloc(
     "vc-i64emu-strict-report-alloc", cl::init(false), cl::Hidden,
     cl::desc("strict check will break on 64-bit alloc"));
-static cl::opt<bool> OptStricterFaddr(
-    "vc-i64emu-strict-report-faddr", cl::init(false), cl::Hidden,
-    cl::desc("strict check will break on 64-bit faddr"));
 static cl::opt<bool>
     OptStricterConst("vc-i64emu-strict-const", cl::init(false), cl::Hidden,
                      cl::desc("strict check will break on 64-bit constanti"));
@@ -1648,8 +1645,6 @@ bool GenXEmulate::Emu64Expander::hasStrictEmulationRequirement(
     return OptStricterOword;
   case GenXIntrinsic::genx_alloca:
     return OptStricterAlloc;
-  case GenXIntrinsic::genx_faddr:
-    return OptStricterFaddr;
   }
 
   switch (Inst->getOpcode()) {

IGC/VectorCompiler/lib/GenXCodeGen/GenXGlobalValueLowering.cpp

@@ -23,8 +23,6 @@ SPDX-License-Identifier: MIT
 ///   4. All paths to global SLM use must start from the same kernel.
 ///
 /// For any other global values relocations are used.
-/// In vISA relocations are enabled via faddr instruction:
-/// faddr very_important_data V1(0,0)<1>
 /// For global value symbols (global variable or function) LLVM IR
 /// represintation of this instruction is:
 /// %g = call i64 @llvm.genx.gaddr.i64.p0a8i8([8 x i8]* @very_important_data)

IGC/VectorCompiler/lib/GenXCodeGen/GenXPatternMatch.cpp

@@ -2409,13 +2409,6 @@ bool GenXPatternMatch::simplifyWrRegion(CallInst *Inst) {
     if (!isa<UndefValue>(OldV))
       return false;
 
-    // have to keep faddr's wrregion to ensure faddr's proper baling
-    auto *Parent = NewV;
-    while (isa<BitCastInst>(Parent))
-      Parent = cast<Instruction>(Parent)->getOperand(0);
-    if (vc::getAnyIntrinsicID(Parent) == GenXIntrinsic::genx_faddr)
-      return false;
-
     if (NewVTy->isVectorTy() &&
         cast<IGCLLVM::FixedVectorType>(NewVTy)->getNumElements() > 1)
       return false;

IGC/VectorCompiler/lib/GenXCodeGen/GenXUtil.h

@@ -584,7 +584,7 @@ bool isWrPredRegionLegalSetP(const CallInst &WrPredRegion);
 // Many of our analyzes do not check whether a function F's user
 // which is a CallInst calls exactly F. This may not be true
 // when a function pointer is passed as an argument of a call to
-// another function, e.g. genx.faddr intrinsic.
+// another function.
 // Returns V casted to CallInst if the check is true,
 // nullptr otherwise.
 const CallInst *checkFunctionCall(const Value *V, const Function *F);