Disable SIMDCF for multi-use EM instructions

For instruction with multiply input:
if it use more than one EM - it is incorrect.
For such instructions - we will deoptimize SIMDCF

Author: igorban-intel

IGC/VectorCompiler/lib/GenXCodeGen/GenXSimdCFConformance.cpp

@@ -281,6 +281,7 @@ class GenXSimdCFConformance {
   SetVector<SimpleValue> EMVals;
   std::map<CallInst *, SetVector<SimpleValue>> RMVals;
   bool lowerSimdCF = false;
+  SmallSet<Instruction *, 32> CrossInsts;
 
 private:
   // GotoJoinEVs: container for goto/join Extract Value (EV) info. Also
@@ -364,6 +365,7 @@ class GenXSimdCFConformance {
     EMProducers.clear();
     LoweredEMValsMap.clear();
     BlocksToOptimize.clear();
+    CrossInsts.clear();
   }
   DominatorTree *getDomTree(Function *F);
 
@@ -852,6 +854,7 @@ void GenXSimdCFConformance::gatherEMVals() {
       if (!isa<Constant>(j->getValue()))
         EMVals.insert(*j);
   }
+  CrossInsts.clear();
 }
 
 /***********************************************************************
@@ -882,6 +885,7 @@ void GenXSimdCFConformance::gatherRMVals() {
           RMValsEntry->insert(*j);
     }
   }
+  CrossInsts.clear();
 }
 
 /***********************************************************************
@@ -2753,6 +2757,12 @@ bool GenXSimdCFConformance::getConnectedVals(
   for (auto ui = Val.getValue()->use_begin(), ue = Val.getValue()->use_end();
        ui != ue; ++ui) {
     auto User = cast<Instruction>(ui->getUser());
+    // Can't have 2 difference EMs in one instruction
+    if (!isa<PHINode>(User) && !isa<CallInst>(User) &&
+        !isa<ExtractValueInst>(User) && !CrossInsts.insert(User).second) {
+      LLVM_DEBUG(dbgs() << "Found multy-EM use instruction:\n" << *User);
+      lowerSimdCF = true;
+    }
     LLVM_DEBUG(dbgs() << "getConnectedVals: -> geted " << *User << "\n");
     if (auto Phi = dyn_cast<PHINode>(User)) {
       // Use in phi node. Add the phi result.

IGC/VectorCompiler/test/GenXEarlySimdCFConformance/conformance-deoptimize.ll

@@ -0,0 +1,34 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2022 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+;
+; RUN: opt %use_old_pass_manager% -GenXEarlySimdCFConformance -march=genx64 -mtriple=spir64-unknown-unknown  -mcpu=Gen9 -S < %s | FileCheck %s
+; ------------------------------------------------
+; GenXEarlySimdCFConformance
+; ------------------------------------------------
+
+; CHECK: foo
+; CHECK-NOT: = tail call {.*}simdcf.goto
+define spir_kernel void @foo() {
+.afterjoin.i.i72:
+  %goto.extractem145.i.i69 = extractvalue { <32 x i1>, <32 x i1>, i1 } zeroinitializer, 0
+  br label %if.then5.i.vec32.i.i118
+
+if.then5.i.vec32.i.i118:                          ; preds = %.afterjoin.i.i72
+  %goto.i.i.i114 = tail call { <32 x i1>, <32 x i1>, i1 } @llvm.genx.simdcf.goto.v32i1.v32i1(<32 x i1> %goto.extractem145.i.i69, <32 x i1> zeroinitializer, <32 x i1> zeroinitializer)
+  %goto.extractem.i.i.i115 = extractvalue { <32 x i1>, <32 x i1>, i1 } zeroinitializer, 0
+  br label %if.end.thread.vec32.i.i.i131
+
+if.end.thread.vec32.i.i.i131:                     ; preds = %if.then5.i.vec32.i.i118
+; Here select with 2 em-inputs - will be deoptimized
+  %0 = select <32 x i1> %goto.extractem145.i.i69, <32 x i1> %goto.extractem145.i.i69, <32 x i1> zeroinitializer
+  ret void
+}
+
+declare { <32 x i1>, <32 x i1>, i1 } @llvm.genx.simdcf.goto.v32i1.v32i1(<32 x i1>, <32 x i1>, <32 x i1>)
+
+attributes #0 = { nofree nosync nounwind readnone speculatable willreturn }