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Fix @llvm.trap intrinsic lowering in VC
The `@llvm.trap` intrinsic is lowered into EOT message to Gateway or Thread Spawned, depending on the target platform.
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3 files changed

+104
-20
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3 files changed

+104
-20
lines changed

IGC/VectorCompiler/lib/GenXCodeGen/GenXLowering.cpp

Lines changed: 24 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -4698,26 +4698,30 @@ bool GenXLowering::lowerUSubWithSat(CallInst *CI) {
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bool GenXLowering::lowerTrap(CallInst *CI) {
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Module *M = CI->getModule();
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IRBuilder<> Builder(CI);
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auto &Ctx = CI->getContext();
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unsigned EMWidth = 32;
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Type *ArgTypes[] = {
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IGCLLVM::FixedVectorType::get(Type::getInt1Ty(Ctx), EMWidth),
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IGCLLVM::FixedVectorType::get(Type::getInt16Ty(Ctx), EMWidth)};
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auto Fn = GenXIntrinsic::getGenXDeclaration(M,
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GenXIntrinsic::genx_raw_send_noresult, ArgTypes);
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SmallVector<Value *, 8> Args;
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// send
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Args.push_back(ConstantInt::get(Type::getInt32Ty(Ctx), 0));
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// predicate all lanes
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Args.push_back(ConstantVector::getSplat(IGCLLVM::getElementCount(EMWidth),
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ConstantInt::getTrue(Ctx)));
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// EOT
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Args.push_back(ConstantInt::get(Type::getInt32Ty(Ctx), 0x27));
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Args.push_back(ConstantInt::get(Type::getInt32Ty(Ctx), 0x02000010));
4717-
Args.push_back(
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ConstantVector::getSplat(IGCLLVM::getElementCount(EMWidth),
4719-
Constant::getNullValue(Type::getInt16Ty(Ctx))));
4720-
Builder.CreateCall(Fn, Args);
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4702+
constexpr unsigned Width = 8;
4703+
auto *PayloadTy = IGCLLVM::FixedVectorType::get(Builder.getInt32Ty(), Width);
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auto *PayloadFunc =
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vc::getAnyDeclaration(M, GenXIntrinsic::genx_r0, {PayloadTy});
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auto *Payload = Builder.CreateCall(PayloadFunc, {});
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SmallVector<Value *, 8> Args{
4709+
Builder.getInt8(2), // modifier (EOT)
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Builder.getInt8(0), // log2(exec size)
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Builder.getTrue(), // predicate
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Builder.getInt8(1), // number of source registers
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Builder.getInt8(ST->hasLSCMessages() ? 3 // Gateway
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: 7), // Thread Spawner
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Builder.getInt32(0), // extened message descriptor
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Builder.getInt32(0x02000010), // message descriptor
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Payload,
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};
4719+
4720+
auto *SendFunc =
4721+
vc::getAnyDeclaration(M, GenXIntrinsic::genx_raw_send2_noresult,
4722+
{Builder.getInt1Ty(), PayloadTy});
4723+
4724+
Builder.CreateCall(SendFunc, Args);
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ToErase.push_back(CI);
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return true;
Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2023 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; RUN: llc %s -march=genx64 -mcpu=XeLP -finalizer-opts='-dumpcommonisa -isaasmToConsole' -o /dev/null \
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; RUN: | FileCheck %s --check-prefix=CHECK
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; RUN: llc %s -march=genx64 -mcpu=XeHPG -finalizer-opts='-dumpcommonisa -isaasmToConsole' -o /dev/null \
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; RUN: | FileCheck %s --check-prefix=CHECK-LSC
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target triple = "genx64-unknown-unknown"
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declare void @llvm.genx.oword.st.v4i32(i32, i32, <4 x i32>)
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declare void @llvm.trap()
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; CHECK: test_trap
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; CHECK: mov (M1, 8) [[PAYLOAD:V[0-9]+]](0,0)<1> %r0(0,0)<1;1,0>
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; CHECK: raw_sends.7.eot.1.0.0 (M1, 1) 0x0:ud 0x2000010:ud [[PAYLOAD]].0 %null.0 %null.0
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; CHECK-LSC: test_trap
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; CHECK-LSC: mov (M1, 8) [[PAYLOAD:V[0-9]+]](0,0)<1> %r0(0,0)<1;1,0>
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; CHECK-LSC: raw_sends.3.eot.1.0.0 (M1, 1) 0x0:ud 0x2000010:ud [[PAYLOAD]].0 %null.0 %null.0
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define spir_kernel void @test_trap(<4 x i32> %arg) local_unnamed_addr #0 {
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%1 = shl <4 x i32> %arg, <i32 3, i32 3, i32 3, i32 3>
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%2 = add <4 x i32> %1, <i32 12, i32 12, i32 12, i32 12>
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tail call void @llvm.trap()
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tail call void @llvm.genx.oword.st.v4i32(i32 1, i32 0, <4 x i32> %2)
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ret void
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}
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attributes #0 = { noinline nounwind "CMGenxMain" }
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!spirv.Source = !{!1}
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!opencl.spir.version = !{!2}
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!opencl.ocl.version = !{!1}
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!opencl.used.extensions = !{!0}
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!opencl.used.optional.core.features = !{!0}
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!spirv.Generator = !{!3}
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!genx.kernels = !{!4}
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!genx.kernel.internal = !{!8}
47+
48+
!0 = !{}
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!1 = !{i32 0}
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!2 = !{i32 1, i32 1}
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!3 = !{i16 6, i16 14}
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!4 = !{void (<4 x i32>)* @test_trap, !"test_trap", !5, i32 0, !6, !1, !7, i32 0}
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!5 = !{i32 1}
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!6 = !{i32 64}
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!7 = !{!"buffer_t"}
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!8 = !{void (<4 x i32>)* @test_trap, null, null, null, null}
Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2023 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; RUN: opt %use_old_pass_manager% -GenXLowering -march=genx64 -mcpu=XeLP -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s
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; RUN: opt %use_old_pass_manager% -GenXLowering -march=genx64 -mcpu=XeHPG -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s --check-prefix=CHECK-LSC
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; RUN: opt %use_old_pass_manager% -GenXLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s --check-prefix=CHECK-LSC-SIMD16
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13+
declare void @llvm.trap()
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define spir_func void @test() {
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; CHECK: [[PAYLOAD:%[^ ]+]] = call <8 x i32> @llvm.genx.r0.v8i32()
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; CHECK: call void @llvm.genx.raw.send2.noresult.i1.v8i32(i8 2, i8 0, i1 true, i8 1, i8 7, i32 0, i32 33554448, <8 x i32> [[PAYLOAD]])
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; CHECK-LSC: [[PAYLOAD:%[^ ]+]] = call <8 x i32> @llvm.genx.r0.v8i32()
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; CHECK-LSC: call void @llvm.genx.raw.send2.noresult.i1.v8i32(i8 2, i8 0, i1 true, i8 1, i8 3, i32 0, i32 33554448, <8 x i32> [[PAYLOAD]])
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; CHECK-LSC-SIMD16: [[PAYLOAD:%[^ ]+]] = call <8 x i32> @llvm.genx.r0.v8i32()
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; CHECK-LSC-SIMD16: call void @llvm.genx.raw.send2.noresult.i1.v8i32(i8 2, i8 0, i1 true, i8 1, i8 3, i32 0, i32 33554448, <8 x i32> [[PAYLOAD]])
22+
tail call void @llvm.trap()
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ret void
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}

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