Add new vISA opcode "add3o" for ternary add with overflow condition modifier.

Add new vISA opcode "add3o" for ternary add with overflow condition modifier.

Author: fangliu2020

visa/CISA.l

@@ -292,6 +292,12 @@ add3 {
         return ARITH4_OP;
     }
 
+add3\.o {
+        TRACE("** ADD3O INST");
+        CISAlval.opcode = str2opcode(yytext);
+        return ARITH4_OP;
+    }
+
 bfn"."x[[:xdigit:]]+ {
         TRACE("** BFN INST");
         CISAlval.bfn_info.func_ctrl = (uint8_t)hexToInt(yytext+5, yyleng-5);

visa/CISA.y

@@ -914,6 +914,7 @@ ArithInstruction_3OPND:
 
 
 ArithInstruction_4OPND:
+     //  1         2         3        4             5                    6                    7                     8
      Predicate ARITH4_OP SatModOpt ExecSize VecDstOperand_G_I VecSrcOperand_G_I_IMM VecSrcOperand_G_I_IMM  VecSrcOperand_G_I_IMM
      {
          pBuilder->CISA_create_arith_instruction($1, $2, $3, $4.emask, $4.exec_size,

visa/Common_ISA_util.cpp

@@ -175,6 +175,7 @@ G4_opcode GetGenOpcodeFromVISAOpcode(ISA_Opcode opcode)
         case ISA_DPASW:
             return G4_dpasw;
         case ISA_ADD3:
+        case ISA_ADD3O:
             return G4_add3;
         case ISA_BFN:
             return G4_bfn;

visa/G4Instruction.h

@@ -87,7 +87,7 @@ HANDLE_INST(subb, 2, 1, InstTypeArith, GENX_BDW, ATTR_NONE)
 HANDLE_INST(dp4a, 3, 1, InstTypeArith, GENX_TGLLP, ATTR_NONE)
 HANDLE_INST(dpas,  3, 1, InstTypeArith, XeHP_SDV, ATTR_NONE)
 HANDLE_INST(dpasw, 3, 1, InstTypeArith, XeHP_SDV, ATTR_NONE)
-HANDLE_INST(add3,  3, 1, InstTypeArith, XeHP_SDV, ATTR_NONE)
+HANDLE_INST(add3,  3, 1, InstTypeArith, XeHP_SDV, ATTR_COMMUTATIVE)
 
 
 HANDLE_INST(madm,   3, 1, InstTypeArith, GENX_BDW, ATTR_NONE)

visa/IsaDescription.cpp

@@ -165,7 +165,8 @@ struct ISA_Inst_Info ISA_Inst_Table[ISA_OPCODE_ENUM_SIZE] =
     { ISA_RESERVED_8E,        ISA_Inst_Reserved,   "reserved8e",          0, 0 },
     { ISA_RESERVED_8F,        ISA_Inst_Reserved,   "reserved8f",          0, 0 },
     { ISA_RESERVED_90,        ISA_Inst_Reserved,   "reserved90",          0, 0 },
-    { ISA_MADW,               ISA_Inst_Arith,      "madw",                3, 1 }
+    { ISA_MADW,               ISA_Inst_Arith,      "madw",                3, 1 },
+    { ISA_ADD3O,              ISA_Inst_Arith,      "add3.o",               3, 1 }
 };
 
 
@@ -1787,6 +1788,18 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] =
         {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD | ISA_TYPE_D, 0},
     },
     },
+
+    /// 146 (0x92)
+    { ALL, ISA_ADD3O, ISA_Inst_Arith, "add3.o", 6, SAME_DATA_TYPE,
+    {
+        { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
+        { OPND_PRED, ISA_TYPE_UW, 0 },
+        { OPND_VECTOR_DST_G_I, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
+        { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
+        { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
+        { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
+    },
+    },
 };
 
 static const ISA_SubInst_Desc VASubOpcodeDesc[] =

visa/IsaVerification.cpp

@@ -1609,6 +1609,7 @@ void vISAVerifier::verifyInstructionArith(
         REPORT_INSTRUCTION(options, dstType == ISA_TYPE_UD, "%s only supports single UD type", ISA_Inst_Table[opcode].str);
         break;
     case ISA_ADD3:
+    case ISA_ADD3O:
         REPORT_INSTRUCTION(options, dstType == ISA_TYPE_UD || dstType == ISA_TYPE_D ||
             dstType == ISA_TYPE_UW || dstType == ISA_TYPE_W,
             "%s only supports interger D/W type", ISA_Inst_Table[opcode].str);
@@ -1715,6 +1716,7 @@ void vISAVerifier::verifyInstructionArith(
                 ISA_Inst_Table[opcode].str);
             break;
         case ISA_ADD3:
+        case ISA_ADD3O:
             REPORT_INSTRUCTION(options,
                 srcType == ISA_TYPE_D || srcType == ISA_TYPE_UD ||
                 srcType == ISA_TYPE_W || srcType == ISA_TYPE_UW,

visa/VisaToG4/TranslateALU.cpp

@@ -101,6 +101,13 @@ int IR_Builder::translateVISAArithmeticInst(
     }
     else if (ISA_Inst_Table[opcode].n_srcs == 3)
     {
+        if (opcode == ISA_ADD3O)
+        {
+            assert(predOpnd != nullptr && "predicate operand couldn't be nullptr");
+            condMod = createCondMod(Mod_o, predOpnd->getBase(), 0);
+            predOpnd = nullptr;
+        }
+
         // do not check type of sources, float and integer are supported
         createInst(
             predOpnd,

visa/include/visa_igc_common_header.h

@@ -394,6 +394,7 @@ typedef enum {
     ISA_RESERVED_8F        = 0x8F,
     ISA_RESERVED_90        = 0x90,
     ISA_MADW               = 0x91,
+    ISA_ADD3O              = 0x92,
     ISA_NUM_OPCODE,
     ISA_OPCODE_ENUM_SIZE   = 0xFF
 } ISA_Opcode;