Reorganize the tests

Author: fineg74

SYCL/ESIMD/lsc/lsc_predicate.cpp

@@ -31,7 +31,6 @@ template <unsigned SIMDSize> int testAccessor(queue q) {
   auto vec_3 = std::vector<int>(size);
 
   std::iota(vec_0.begin(), vec_0.end(), 0);
-  std::iota(vec_1.begin(), vec_1.end(), 0);
   std::iota(vec_2.begin(), vec_2.end(), 0);
   std::iota(vec_3.begin(), vec_3.end(), 0);
   auto buf_0 = buffer{vec_0};
@@ -81,18 +80,16 @@ template <unsigned SIMDSize> int testAccessor(queue q) {
   }
 
   auto error = 0;
+  int acc = 0;
   for (auto i = 0; i != size; ++i) {
     if (vec_0[i] != 2 * i) {
       ++error;
       std::cout << " Accessor Test 1 out[" << i << "] = 0x" << std::hex
                 << vec_0[i] << " vs etalon = 0x" << 2 * i << std::dec
                 << std::endl;
     }
-    if (vec_1[i] > 0) {
-      ++error;
-      std::cout << " Accessor Test 2 out[" << i << "] = 0x" << std::hex
-                << vec_1[i] << " vs etalon = 0x" << 0 << std::dec << std::endl;
-    }
+    acc += vec_1[i];
+
     if (vec_2[i] != i) {
       ++error;
       std::cout << " Accessor Test 3 out[" << i << "] = 0x" << std::hex
@@ -105,6 +102,11 @@ template <unsigned SIMDSize> int testAccessor(queue q) {
                 << vec_3[i] << " vs etalon = 0x" << i << std::dec << std::endl;
     }
   }
+  if (acc == 0) {
+    ++error;
+    std::cout << " Accessor Test 2 out = 0"
+              << " vs etalon non 0" << std::endl;
+  }
   std::cout << "Accessor lsc predicate test ";
   std::cout << (error != 0 ? "FAILED" : "passed") << std::endl;
   return error;
@@ -118,10 +120,13 @@ template <unsigned SIMDSize> int testUSM(queue q) {
   auto *vec_2 = malloc_shared<int>(size, q);
   auto *vec_3 = malloc_shared<int>(size, q);
   std::iota(vec_0, vec_0 + size, 0);
-  std::iota(vec_1, vec_1 + size, 0);
   std::iota(vec_2, vec_2 + size, 0);
   std::iota(vec_3, vec_3 + size, 0);
 
+  for (int i = 0; i < size; ++i) {
+    vec_1[i] = 0;
+  }
+
   try {
     q.submit([&](handler &h) {
       h.parallel_for(
@@ -162,17 +167,15 @@ template <unsigned SIMDSize> int testUSM(queue q) {
   }
 
   int error = 0;
+  int acc = 0;
   for (auto i = 0; i != size; ++i) {
     if (vec_0[i] != 2 * i) {
       ++error;
       std::cout << " USM Test 1 out[" << i << "] = 0x" << std::hex << vec_0[i]
                 << " vs etalon = 0x" << 2 * i << std::dec << std::endl;
     }
-    if (vec_1[i] > 0) {
-      ++error;
-      std::cout << " USM Test 2 out[" << i << "] = 0x" << std::hex << vec_1[i]
-                << " vs etalon = 0x" << 0 << std::dec << std::endl;
-    }
+    acc += vec_1[i];
+
     if (vec_2[i] != i) {
       ++error;
       std::cout << " USM Test 3 out[" << i << "] = 0x" << std::hex << vec_2[i]
@@ -185,6 +188,11 @@ template <unsigned SIMDSize> int testUSM(queue q) {
                 << " vs etalon = 0x" << i << std::dec << std::endl;
     }
   }
+  if (acc == 0) {
+    ++error;
+    std::cout << " USM Test 2 out = 0"
+              << " vs etalon non 0" << std::endl;
+  }
   sycl::free(vec_0, q);
   sycl::free(vec_1, q);
   sycl::free(vec_2, q);

SYCL/ESIMD/lsc/lsc_predicate_stateless.cpp

@@ -33,7 +33,6 @@ template <unsigned SIMDSize> int testAccessor(queue q) {
   auto vec_3 = std::vector<int>(size);
 
   std::iota(vec_0.begin(), vec_0.end(), 0);
-  std::iota(vec_1.begin(), vec_1.end(), 0);
   std::iota(vec_2.begin(), vec_2.end(), 0);
   std::iota(vec_3.begin(), vec_3.end(), 0);
   auto buf_0 = buffer{vec_0};
@@ -83,6 +82,7 @@ template <unsigned SIMDSize> int testAccessor(queue q) {
     return 1;
   }
 
+  int acc = 0;
   auto error = 0;
   for (auto i = 0; i != size; ++i) {
     if (vec_0[i] != 2 * i) {
@@ -91,11 +91,8 @@ template <unsigned SIMDSize> int testAccessor(queue q) {
                 << vec_0[i] << " vs etalon = 0x" << 2 * i << std::dec
                 << std::endl;
     }
-    if (vec_1[i] > 0) {
-      ++error;
-      std::cout << " Accessor Test 2 out[" << i << "] = 0x" << std::hex
-                << vec_1[i] << " vs etalon = 0x" << 0 << std::dec << std::endl;
-    }
+    acc += vec_1[i];
+
     if (vec_2[i] != i) {
       ++error;
       std::cout << " Accessor Test 3 out[" << i << "] = 0x" << std::hex
@@ -108,6 +105,11 @@ template <unsigned SIMDSize> int testAccessor(queue q) {
                 << vec_3[i] << " vs etalon = 0x" << i << std::dec << std::endl;
     }
   }
+  if (acc == 0) {
+    ++error;
+    std::cout << " Accessor Test 2 out = 0"
+              << " vs etalon is non zero." << std::endl;
+  }
   std::cout << "Accessor lsc predicate test ";
   std::cout << (error != 0 ? "FAILED" : "passed") << std::endl;
   return error;