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Address the atomics' macro rework: emulation runs by default #104
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AGindinson
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@AGindinson, please, do not force-push commits to PR branch! |
Sorry, those were very minor edits. Relying on the "squash and merge" from now on. |
It doesn't matter. You make reviewers miserable - while I was commenting on old commit, you removed it and GitHub doesn't let me to add a comment for non-existing commit, so I had re-do my work. It not a big deal for one comment, but it should be avoided to not lose reviewers comments in the future. |
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Signed-off-by: Artem Gindinson <[email protected]>
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Signed-off-by: Artem Gindinson <[email protected]>
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Signed-off-by: Artem Gindinson <[email protected]>
AlexeySotkin
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The new EXT/SPV_EXT_shader_atomic_float_add SPIR-V extension allows us to further specialize `atomic::fetch_add()` for floating point types. In device mode, we'll now be creating an external call to a built-in-like `__spirv_AtomicFAddEXT()`. This is similar to what is done for other atomic binary instructions, e.g. the integer specialization of `fetch_add()` being mapped onto `__spirv_AtomicIAdd()`. Furthermore, `atomic::fetch_sub()` is also re-implemented to use `__spirv_AtomicFAddEXT()`, the added operand being a negation of the original one. Tests for the feature have been finalized in intel/llvm-test-suite#104. Signed-off-by: Artem Gindinson <[email protected]>
Signed-off-by: Artem Gindinson <[email protected]>
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The new EXT/SPV_EXT_shader_atomic_float_add SPIR-V extension allows us to further specialize atomic::fetch_add() for floating point types. In device mode, we'll now be creating an external call to a built-in-like __spirv_AtomicFAddEXT(). This is similar to what is done for other atomic binary instructions, e.g. the integer specialization of fetch_add() being mapped onto __spirv_AtomicIAdd(). Furthermore, atomic::fetch_sub() is also re-implemented to use __spirv_AtomicFAddEXT(), the added operand being a negation of the original one. The new implementation can be exposed if a dedicated macro is defined: SYCL_USE_NATIVE_FP_ATOMICS. Otherwise, a fallback is used, where the atomic operation is done via spinlock emulation. At the moment of committing this, only Intel GPUs support the "native" implementation, which relies on a SPIR-V extension. Tests for the feature have been finalized in intel/llvm-test-suite#104. Signed-off-by: Artem Gindinson [email protected]
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A follow-up to intel#104 that will set up the infrastructure for min/max implementation changes. The native tests will be temporarily disabled on all targets, and then enabled in steps (hence `UNSUPPORTED: *` is not a good choice). Signed-off-by: Artem Gindinson <[email protected]>
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A follow-up to #104 that will set up the infrastructure for min/max implementation changes. The native tests will be temporarily disabled on all targets, and then enabled in steps (hence `UNSUPPORTED: *` is not a good choice). Signed-off-by: Artem Gindinson <[email protected]>
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…lvm-test-suite#104) Signed-off-by: Artem Gindinson <[email protected]>
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Signed-off-by: Artem Gindinson [email protected]