Skip to content
This repository was archived by the owner on Mar 28, 2023. It is now read-only.

[SYCL][ESIMD] Add tests for new raw send{s} API #1664

Merged
merged 1 commit into from
Mar 18, 2023
Merged

[SYCL][ESIMD] Add tests for new raw send{s} API #1664

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
13 changes: 10 additions & 3 deletions SYCL/ESIMD/histogram_raw_send.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,10 @@
// REQUIRES: gpu-intel-gen9
// UNSUPPORTED: gpu-intel-dg1,gpu-intel-dg2,cuda,hip, gpu-intel-pvc
// UNSUPPORTED: ze_debug-1,ze_debug4
// RUN: %clangxx -fsycl %s -o %t.out
// RUN: %GPU_RUN_PLACEHOLDER %t.out
// RUN: %clangxx -fsycl %s -o %t1.out
// RUN: %GPU_RUN_PLACEHOLDER %t1.out
// RUN: %clangxx -fsycl -DNEW_API %s -o %t2.out
// RUN: %GPU_RUN_PLACEHOLDER %t2.out

// The test checks raw send functionality with atomic write implementation
// on SKL. It does not work on DG1 due to send instruction incompatibility.
Expand Down Expand Up @@ -85,10 +87,15 @@ ESIMD_INLINE void atomic_write(T *bins, simd<unsigned, n> offset,
constexpr uint8_t numSrc1 = 0x1;
constexpr uint8_t isEOT = 0;
constexpr uint8_t isSendc = 0;

#ifdef NEW_API
experimental::esimd::raw_sends(oldDst, vAddr, src0, exDesc, desc, execSize,
sfid, numSrc0, numSrc1, numDst, isEOT, isSendc,
pred);
#else
experimental::esimd::raw_sends_load(oldDst, vAddr, src0, exDesc, desc,
execSize, sfid, numSrc0, numSrc1, numDst,
isEOT, isSendc, pred);
#endif
}

int main(int argc, char *argv[]) {
Expand Down
24 changes: 19 additions & 5 deletions SYCL/ESIMD/vadd_raw_send.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,10 @@
// UNSUPPORTED: gpu-intel-dg1,gpu-intel-dg2,cuda,hip
// TODO: esimd_emulator fails due to unimplemented 'raw_send' intrinsic
// XFAIL: esimd_emulator
// RUN: %clangxx -fsycl %s -o %t.out
// RUN: %GPU_RUN_PLACEHOLDER %t.out
// RUN: %clangxx -fsycl %s -o %t1.out
// RUN: %GPU_RUN_PLACEHOLDER %t1.out
// RUN: %clangxx -fsycl -DNEW_API %s -o %t2.out
// RUN: %GPU_RUN_PLACEHOLDER %t2.out

// The test checks raw send functionality with block read/write implementation
// on SKL. It does not work on DG1 due to send instruction incompatibility.
Expand Down Expand Up @@ -41,9 +43,13 @@ ESIMD_INLINE simd<T, N> dwaligned_block_read(AccessorTy acc,
constexpr uint8_t sfid = 0x0;
constexpr uint8_t numSrc0 = 0x1;
constexpr uint8_t numDst = 0x2;

#ifdef NEW_API
return experimental::esimd::raw_send(oldDst, src0, exDesc, desc, execSize,
sfid, numSrc0, numDst);
#else
return experimental::esimd::raw_send_load(oldDst, src0, exDesc, desc,
execSize, sfid, numSrc0, numDst);
#endif
}

template <typename T, int N, typename AccessorTy>
Expand All @@ -59,9 +65,13 @@ ESIMD_INLINE void block_write1(AccessorTy acc, unsigned int offset,
constexpr uint8_t sfid = 0x0;
constexpr uint8_t numSrc0 = 0x1;
constexpr uint8_t numSrc1 = 0x1;

#ifdef NEW_API
return experimental::esimd::raw_sends(src0, data, exDesc, desc, execSize,
sfid, numSrc0, numSrc1);
#else
return experimental::esimd::raw_sends_store(src0, data, exDesc, desc,
execSize, sfid, numSrc0, numSrc1);
#endif
}

template <typename T, int N, typename AccessorTy>
Expand All @@ -80,9 +90,13 @@ ESIMD_INLINE void block_write2(AccessorTy acc, unsigned int offset,
constexpr uint8_t execSize = 0x83;
constexpr uint8_t sfid = 0x0;
constexpr uint8_t numSrc0 = 0x2;

#ifdef NEW_API
return experimental::esimd::raw_send(src0, exDesc, desc, execSize, sfid,
numSrc0);
#else
return experimental::esimd::raw_send_store(src0, exDesc, desc, execSize, sfid,
numSrc0);
#endif
}

int main(void) {
Expand Down