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[SYCL] [FPGA] Update latency control E2E tests #982

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Apr 28, 2022
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[SYCL] [FPGA] Update latency control E2E tests #982

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1c6dbd7
Update latency control E2E tests
shuoniu-intel Apr 8, 2022
f77ab75
Update the namespace of latency control properties
shuoniu-intel Apr 19, 2022
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15 changes: 10 additions & 5 deletions SYCL/Basic/fpga_tests/fpga_latency_control_lsu.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -40,11 +40,16 @@ int test_latency_control(queue Queue) {
auto in_ptr = input_accessor.get_pointer();
auto out_ptr = output_accessor.get_pointer();

float value = PrefetchingLSU::load<
ext::intel::experimental::latency_anchor_id<0>>(in_ptr);

BurstCoalescedLSU::store<ext::intel::experimental::latency_constraint<
0, ext::intel::experimental::type::exact, 5>>(out_ptr, value);
float value = PrefetchingLSU::load(
in_ptr, ext::oneapi::experimental::properties(
ext::intel::experimental::latency_anchor_id<0>));

BurstCoalescedLSU::store(
out_ptr, value,
ext::oneapi::experimental::properties(
ext::intel::experimental::latency_constraint<
0, ext::intel::experimental::latency_control_type::exact,
5>));
});
});
}
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16 changes: 10 additions & 6 deletions SYCL/Basic/fpga_tests/fpga_latency_control_pipe.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -34,12 +34,16 @@ int test_latency_control(queue Queue) {
cgh.single_task<class kernel>([=] {
Pipe1::write(input_accessor[0]);

int value =
Pipe1::read<ext::intel::experimental::latency_anchor_id<0>>();

Pipe2::write<ext::intel::experimental::latency_anchor_id<1>,
ext::intel::experimental::latency_constraint<
0, ext::intel::experimental::type::exact, 2>>(value);
int value = Pipe1::read(ext::oneapi::experimental::properties(
ext::intel::experimental::latency_anchor_id<0>));

Pipe2::write(
value,
ext::oneapi::experimental::properties(
ext::intel::experimental::latency_anchor_id<1>,
ext::intel::experimental::latency_constraint<
0, ext::intel::experimental::latency_control_type::exact,
2>));

output_accessor[0] = Pipe2::read();
});
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