|
| 1 | +; Generated with: |
| 2 | +; source.cl: |
| 3 | +; void __spirv_Subgroup2DBlockLoadINTEL( int element_size, int block_width, int block_height, int block_count, const __global void* src_base_pointer, int memory_width, int memory_height, int memory_pitch, int2 coordinate, private void* dst_pointer); |
| 4 | +; void __spirv_Subgroup2DBlockLoadTransposeINTEL(int element_size, int block_width, int block_height, int block_count, const __global void* src_base_pointer, int memory_width, int memory_height, int memory_pitch, int2 coordinate, private void* dst_pointer); |
| 5 | +; void __spirv_Subgroup2DBlockLoadTransformINTEL(int element_size, int block_width, int block_height, int block_count, const __global void* src_base_pointer, int memory_width, int memory_height, int memory_pitch, int2 coordinate, private void* dst_pointer); |
| 6 | +; void __spirv_Subgroup2DBlockPrefetchINTEL( int element_size, int block_width, int block_height, int block_count, const __global void* src_base_pointer, int memory_width, int memory_height, int memory_pitch, int2 coordinate ); |
| 7 | +; void __spirv_Subgroup2DBlockStoreINTEL( int element_size, int block_width, int block_height, int block_count, const private void* src_pointer, __global void* dst_base_pointer, int memory_width, int memory_height, int memory_pitch, int2 coordinate ); |
| 8 | +; |
| 9 | +; void foo(const __global void* base_address, __global void* dst_base_pointer, int width, int height, int pitch, int2 coord, private void* dst_pointer, const private void* src_pointer) { |
| 10 | +; const int i = 42; |
| 11 | +; __spirv_Subgroup2DBlockLoadINTEL(i, i, i, i, base_address, width, height, pitch, coord, dst_pointer); |
| 12 | +; __spirv_Subgroup2DBlockLoadTransformINTEL(i, i, i, i, base_address, width, height, pitch, coord, dst_pointer); |
| 13 | +; __spirv_Subgroup2DBlockLoadTransposeINTEL(i, i, i, i, base_address, width, height, pitch, coord, dst_pointer); |
| 14 | +; __spirv_Subgroup2DBlockPrefetchINTEL(i, i, i, i, base_address, width, height, pitch, coord); |
| 15 | +; __spirv_Subgroup2DBlockStoreINTEL(i, i, i, i, src_pointer, dst_base_pointer, width, height, pitch, coord); |
| 16 | +; } |
| 17 | +; clang -cc1 -cl-std=clc++2021 -triple spir64-unknown-unknown -emit-llvm -finclude-default-header source.cl -o tmp.ll |
| 18 | + |
| 19 | +; RUN: llvm-as %s -o %t.bc |
| 20 | +; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_INTEL_2d_block_io |
| 21 | +; RUN: llvm-spirv %t.spv -o %t.spt --to-text |
| 22 | +; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV |
| 23 | + |
| 24 | +; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR |
| 25 | +; RUN: llvm-dis %t.rev.bc -o %t.rev.ll |
| 26 | +; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM |
| 27 | + |
| 28 | +; RUN: not llvm-spirv %t.bc 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR |
| 29 | +; CHECK-ERROR: RequiresExtension: Feature requires the following SPIR-V extension: |
| 30 | +; CHECK-ERROR-NEXT: SPV_INTEL_2d_block_io |
| 31 | + |
| 32 | +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" |
| 33 | +target triple = "spir64-unknown-unknown" |
| 34 | + |
| 35 | +; CHECK-SPIRV: Capability Subgroup2DBlockIOINTEL |
| 36 | +; CHECK-SPIRV: Capability Subgroup2DBlockTransformINTEL |
| 37 | +; CHECK-SPIRV: Capability Subgroup2DBlockTransposeINTEL |
| 38 | +; CHECK-SPIRV: Extension "SPV_INTEL_2d_block_io" |
| 39 | +; CHECK-SPIRV-DAG: TypeInt [[#Int8Ty:]] 8 0 |
| 40 | +; CHECK-SPIRV-DAG: TypeInt [[#Int32Ty:]] 32 0 |
| 41 | +; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#Const42:]] 42 |
| 42 | +; CHECK-SPIRV-DAG: TypeVoid [[#VoidTy:]] |
| 43 | +; CHECK-SPIRV-DAG: TypePointer [[#GlbPtrTy:]] 5 [[#Int8Ty]] |
| 44 | +; CHECK-SPIRV-DAG: TypeVector [[#VectorTy:]] [[#Int32Ty]] 2 |
| 45 | +; CHECK-SPIRV-DAG: TypePointer [[#PrvPtrTy:]] 7 [[#Int8Ty]] |
| 46 | +; CHECK-SPIRV: FunctionParameter [[#GlbPtrTy]] [[#BaseSrc:]] |
| 47 | +; CHECK-SPIRV: FunctionParameter [[#GlbPtrTy]] [[#BaseDst:]] |
| 48 | +; CHECK-SPIRV: FunctionParameter [[#Int32Ty]] [[#Width:]] |
| 49 | +; CHECK-SPIRV: FunctionParameter [[#Int32Ty]] [[#Height:]] |
| 50 | +; CHECK-SPIRV: FunctionParameter [[#Int32Ty]] [[#Pitch:]] |
| 51 | +; CHECK-SPIRV: FunctionParameter [[#VectorTy]] [[#Coord:]] |
| 52 | +; CHECK-SPIRV: FunctionParameter [[#PrvPtrTy]] [[#Dst:]] |
| 53 | +; CHECK-SPIRV: FunctionParameter [[#PrvPtrTy]] [[#Src:]] |
| 54 | +; CHECK-SPIRV: Subgroup2DBlockLoadINTEL [[#Const42]] [[#Const42]] [[#Const42]] [[#Const42]] [[#BaseSrc]] [[#Width]] [[#Height]] [[#Pitch]] [[#Coord]] [[#Dst]] |
| 55 | +; CHECK-SPIRV: Subgroup2DBlockLoadTransformINTEL [[#Const42]] [[#Const42]] [[#Const42]] [[#Const42]] [[#BaseSrc]] [[#Width]] [[#Height]] [[#Pitch]] [[#Coord]] [[#Dst]] |
| 56 | +; CHECK-SPIRV: Subgroup2DBlockLoadTransposeINTEL [[#Const42]] [[#Const42]] [[#Const42]] [[#Const42]] [[#BaseSrc]] [[#Width]] [[#Height]] [[#Pitch]] [[#Coord]] [[#Dst]] |
| 57 | +; CHECK-SPIRV: Subgroup2DBlockPrefetchINTEL [[#Const42]] [[#Const42]] [[#Const42]] [[#Const42]] [[#BaseSrc]] [[#Width]] [[#Height]] [[#Pitch]] [[#Coord]] |
| 58 | +; CHECK-SPIRV: Subgroup2DBlockStoreINTEL [[#Const42]] [[#Const42]] [[#Const42]] [[#Const42]] [[#Src]] [[#BaseDst]] [[#Width]] [[#Height]] [[#Pitch]] [[#Coord]] |
| 59 | + |
| 60 | +; CHECK-LLVM: call spir_func void @_Z32__spirv_Subgroup2DBlockLoadINTELiiiiPU3AS1ciiiDv2_iPc(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, <2 x i32> %{{.*}}, ptr %{{.*}}) |
| 61 | +; CHECK-LLVM: call spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransformINTELiiiiPU3AS1ciiiDv2_iPc(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, <2 x i32> %{{.*}}, ptr %{{.*}}) |
| 62 | +; CHECK-LLVM: call spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransposeINTELiiiiPU3AS1ciiiDv2_iPc(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, <2 x i32> %{{.*}}, ptr %{{.*}}) |
| 63 | +; CHECK-LLVM: call spir_func void @_Z36__spirv_Subgroup2DBlockPrefetchINTELiiiiPU3AS1ciiiDv2_i(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, <2 x i32> %{{.*}}) |
| 64 | +; CHECK-LLVM: call spir_func void @_Z33__spirv_Subgroup2DBlockStoreINTELiiiiPcPU3AS1ciiiDv2_i(i32 42, i32 42, i32 42, i32 42, ptr %{{.*}}, ptr addrspace(1) %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, <2 x i32> %{{.*}}) |
| 65 | + |
| 66 | +define spir_func void @foo(ptr addrspace(1) %base_address, ptr addrspace(1) %dst_base_pointer, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord, ptr %dst_pointer, ptr %src_pointer) { |
| 67 | +entry: |
| 68 | + call spir_func void @_Z32__spirv_Subgroup2DBlockLoadINTELiiiiPU3AS1KviiiDv2_iPv(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %base_address, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord, ptr %dst_pointer) |
| 69 | + call spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransformINTELiiiiPU3AS1KviiiDv2_iPv(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %base_address, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord, ptr %dst_pointer) |
| 70 | + call spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransposeINTELiiiiPU3AS1KviiiDv2_iPv(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %base_address, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord, ptr %dst_pointer) |
| 71 | + call spir_func void @_Z36__spirv_Subgroup2DBlockPrefetchINTELiiiiPU3AS1KviiiDv2_i(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %base_address, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord) |
| 72 | + call spir_func void @_Z33__spirv_Subgroup2DBlockStoreINTELiiiiPKvPU3AS1viiiDv2_i(i32 42, i32 42, i32 42, i32 42, ptr %src_pointer, ptr addrspace(1) %dst_base_pointer, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord) |
| 73 | + ret void |
| 74 | +} |
| 75 | + |
| 76 | +declare spir_func void @_Z32__spirv_Subgroup2DBlockLoadINTELiiiiPU3AS1KviiiDv2_iPv(i32, i32, i32, i32, ptr addrspace(1), i32, i32, i32, <2 x i32>, ptr) |
| 77 | +declare spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransformINTELiiiiPU3AS1KviiiDv2_iPv(i32, i32, i32, i32, ptr addrspace(1), i32, i32, i32, <2 x i32>, ptr) |
| 78 | +declare spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransposeINTELiiiiPU3AS1KviiiDv2_iPv(i32, i32, i32, i32, ptr addrspace(1), i32, i32, i32, <2 x i32>, ptr) |
| 79 | +declare spir_func void @_Z36__spirv_Subgroup2DBlockPrefetchINTELiiiiPU3AS1KviiiDv2_i(i32, i32, i32, i32, ptr addrspace(1), i32, i32, i32, <2 x i32>) |
| 80 | +declare spir_func void @_Z33__spirv_Subgroup2DBlockStoreINTELiiiiPKvPU3AS1viiiDv2_i(i32, i32, i32, i32, ptr, ptr addrspace(1), i32, i32, i32, <2 x i32>) |
| 81 | + |
| 82 | +!opencl.spir.version = !{!0} |
| 83 | +!spirv.Source = !{!1} |
| 84 | +!llvm.ident = !{!2} |
| 85 | + |
| 86 | +!0 = !{i32 1, i32 0} |
| 87 | +!1 = !{i32 4, i32 100000} |
| 88 | +!2 = !{!"clang version 17.0.0"} |
0 commit comments