We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent d55067f commit 2c931ffCopy full SHA for 2c931ff
llvm-spirv/test/FPFastMathModeNotNaNFast.spvasm
@@ -13,9 +13,10 @@
13
OpName %r3 "r3"
14
OpName %r4 "r4"
15
OpName %r5 "r5"
16
+ OpName %r6 "r6"
17
OpDecorate %dec FPFastMathMode NotNaN|Fast
18
%dec = OpDecorationGroup
- OpGroupDecorate %dec %r1 %r2 %r3 %r4 %r5
19
+ OpGroupDecorate %dec %r1 %r2 %r3 %r4 %r5 %r6
20
%void = OpTypeVoid
21
%float = OpTypeFloat 32
22
%5 = OpTypeFunction %void %float %float
@@ -28,6 +29,7 @@
28
29
%r3 = OpFMul %float %a %b
30
%r4 = OpFDiv %float %a %b
31
%r5 = OpFRem %float %a %b
32
+ %r6 = OpFNegate %float %a
33
OpReturn
34
OpFunctionEnd
35
@@ -36,3 +38,4 @@
36
38
; CHECK: %r3 = fmul fast float %a, %b
37
39
; CHECK: %r4 = fdiv fast float %a, %b
40
; CHECK: %r5 = frem fast float %a, %b
41
+; CHECK: %r6 = fneg fast float %a
llvm-spirv/test/OpFNegate.spvasm
0 commit comments