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[SPIR][InstCombine] Work around SPIR-V translator limitation (#2143)
This is temporary work-around for a problem reported here: KhronosGroup/SPIRV-LLVM-Translator#645 InstCombine canonical form for this pattern ``` // Example (little endian): // trunc (extractelement <4 x i64> %X, 0) to i32 // ---> // extractelement <8 x i32> (bitcast <4 x i64> %X to <8 x i32>), i32 0 ``` can't be lowered by SPIR-V translator to "standard" format.
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llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp

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@@ -862,6 +862,20 @@ Instruction *InstCombiner::visitTrunc(TruncInst &Trunc) {
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if (Instruction *I = foldVecTruncToExtElt(Trunc, *this))
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return I;
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// FIXME: This is temporary work-around for a problem reported here:
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// https://github.com/KhronosGroup/SPIRV-LLVM-Translator/issues/645
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//
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// InstCombine canonical form for this pattern
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// ```
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// // Example (little endian):
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// // trunc (extractelement <4 x i64> %X, 0) to i32
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// // --->
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// // extractelement <8 x i32> (bitcast <4 x i64> %X to <8 x i32>), i32 0
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// ```
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// can't be lowered by SPIR-V translator to "standard" format.
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if (StringRef(Trunc.getModule()->getTargetTriple()).startswith("spir"))
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return nullptr;
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// Whenever an element is extracted from a vector, and then truncated,
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// canonicalize by converting it to a bitcast followed by an
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// extractelement.
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; RUN: opt < %s -instcombine -S | FileCheck %s
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target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
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target triple = "spir"
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define i32 @shrinkExtractElt_i64_to_i32_0(<3 x i64> %x) {
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; CHECK-LABEL: @shrinkExtractElt_i64_to_i32_0(
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; CHECK-NOT: [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <6 x i32>
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; CHECK-NOT: [[T:%.*]] = extractelement <6 x i32> [[TMP1]], i32 0
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%e = extractelement <3 x i64> %x, i32 0
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%t = trunc i64 %e to i32
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ret i32 %t
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}

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