Skip to content

Commit 467f5c2

Browse files
vmaksimovladimirlaz
vmaksimo
authored and
vladimirlaz
committed
Translate new set of Intel FPGA Loop Controls
Specification can be found here: KhronosGroup/SPIRV-Registry#62 As per revision C -> revision E transition in the spec, patch introduces translation of the following loop controls: * PipelineDisableINTEL * LoopCoalesceINTEL * MaxInterleavingINTEL * SpeculatedIterationsINTEL Signed-off-by: Viktoria Maksimova <[email protected]>
1 parent 73dd705 commit 467f5c2

File tree

5 files changed

+288
-0
lines changed

5 files changed

+288
-0
lines changed

‎llvm-spirv/lib/SPIRV/SPIRVReader.cpp

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -786,6 +786,47 @@ void SPIRVToLLVM::setLLVMLoopMetadata(const LoopInstType *LM,
786786
Metadata.push_back(llvm::MDNode::get(*Context, Parameters));
787787
}
788788
}
789+
if (LC & LoopControlPipelineEnableINTEL) {
790+
Metadata.push_back(llvm::MDNode::get(
791+
*Context,
792+
getMetadataFromNameAndParameter("llvm.loop.intel.pipelining.enable",
793+
LoopControlParameters[NumParam])));
794+
++NumParam;
795+
assert(NumParam <= LoopControlParameters.size() &&
796+
"Missing loop control parameter!");
797+
}
798+
if (LC & LoopControlLoopCoalesceINTEL) {
799+
if (LoopControlParameters.size()) {
800+
Metadata.push_back(llvm::MDNode::get(
801+
*Context,
802+
getMetadataFromNameAndParameter("llvm.loop.coalesce.count",
803+
LoopControlParameters[NumParam])));
804+
++NumParam;
805+
} else { // If LoopCoalesce has no parameters
806+
Metadata.push_back(llvm::MDNode::get(
807+
*Context, getMetadataFromName("llvm.loop.coalesce.enable")));
808+
}
809+
assert(NumParam <= LoopControlParameters.size() &&
810+
"Missing loop control parameter!");
811+
}
812+
if (LC & LoopControlMaxInterleavingINTEL) {
813+
Metadata.push_back(llvm::MDNode::get(
814+
*Context,
815+
getMetadataFromNameAndParameter("llvm.loop.max_interleaving.count",
816+
LoopControlParameters[NumParam])));
817+
++NumParam;
818+
assert(NumParam <= LoopControlParameters.size() &&
819+
"Missing loop control parameter!");
820+
}
821+
if (LC & LoopControlSpeculatedIterationsINTEL) {
822+
Metadata.push_back(llvm::MDNode::get(
823+
*Context, getMetadataFromNameAndParameter(
824+
"llvm.loop.intel.speculated.iterations.count",
825+
LoopControlParameters[NumParam])));
826+
++NumParam;
827+
assert(NumParam <= LoopControlParameters.size() &&
828+
"Missing loop control parameter!");
829+
}
789830
llvm::MDNode *Node = llvm::MDNode::get(*Context, Metadata);
790831

791832
// Set the first operand to refer itself

‎llvm-spirv/lib/SPIRV/SPIRVWriter.cpp

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -856,6 +856,34 @@ LLVMToSPIRV::getLoopControl(const BranchInst *Branch,
856856
unsigned SafeLen = IVDep.getSafeLen();
857857
for (auto &ArrayId : IVDep.getArrayVariables())
858858
DependencyArrayParameters.emplace_back(ArrayId, SafeLen);
859+
} else if (S == "llvm.loop.intel.pipelining.enable") {
860+
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
861+
BM->addCapability(CapabilityFPGALoopControlsINTEL);
862+
size_t I = getMDOperandAsInt(Node, 1);
863+
Parameters.push_back(I);
864+
LoopControl |= spv::LoopControlPipelineEnableINTEL;
865+
} else if (S == "llvm.loop.coalesce.enable") {
866+
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
867+
BM->addCapability(CapabilityFPGALoopControlsINTEL);
868+
LoopControl |= spv::LoopControlLoopCoalesceINTEL;
869+
} else if (S == "llvm.loop.coalesce.count") {
870+
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
871+
BM->addCapability(CapabilityFPGALoopControlsINTEL);
872+
size_t I = getMDOperandAsInt(Node, 1);
873+
Parameters.push_back(I);
874+
LoopControl |= spv::LoopControlLoopCoalesceINTEL;
875+
} else if (S == "llvm.loop.max_interleaving.count") {
876+
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
877+
BM->addCapability(CapabilityFPGALoopControlsINTEL);
878+
size_t I = getMDOperandAsInt(Node, 1);
879+
Parameters.push_back(I);
880+
LoopControl |= spv::LoopControlMaxInterleavingINTEL;
881+
} else if (S == "llvm.loop.intel.speculated.iterations.count") {
882+
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
883+
BM->addCapability(CapabilityFPGALoopControlsINTEL);
884+
size_t I = getMDOperandAsInt(Node, 1);
885+
Parameters.push_back(I);
886+
LoopControl |= spv::LoopControlSpeculatedIterationsINTEL;
859887
}
860888
}
861889
}

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1066,6 +1066,10 @@ inline bool isValidLoopControlMask(SPIRVWord Mask) {
10661066
ValidMask |= LoopControlInitiationIntervalINTEL;
10671067
ValidMask |= LoopControlMaxConcurrencyINTEL;
10681068
ValidMask |= LoopControlDependencyArrayINTEL;
1069+
ValidMask |= LoopControlPipelineEnableINTEL;
1070+
ValidMask |= LoopControlLoopCoalesceINTEL;
1071+
ValidMask |= LoopControlMaxInterleavingINTEL;
1072+
ValidMask |= LoopControlSpeculatedIterationsINTEL;
10691073

10701074
return (Mask & ~ValidMask) == 0;
10711075
}

‎llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -505,6 +505,10 @@ enum LoopControlMask {
505505
LoopControlInitiationIntervalINTEL = 0x10000,
506506
LoopControlMaxConcurrencyINTEL = 0x20000,
507507
LoopControlDependencyArrayINTEL = 0x40000,
508+
LoopControlPipelineEnableINTEL = 0x80000,
509+
LoopControlLoopCoalesceINTEL = 0x100000,
510+
LoopControlMaxInterleavingINTEL = 0x200000,
511+
LoopControlSpeculatedIterationsINTEL = 0x400000,
508512
};
509513

510514
enum FunctionControlShift {

‎llvm-spirv/test/transcoding/FPGALoopAttr.ll

Lines changed: 211 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -168,6 +168,175 @@ for.end36: ; preds = %for.cond29
168168
ret void
169169
}
170170

171+
; Function Attrs: noinline nounwind optnone
172+
define spir_func void @loop_pipelining() #0 {
173+
entry:
174+
%a = alloca [10 x i32], align 4
175+
%i = alloca i32, align 4
176+
store i32 0, i32* %i, align 4
177+
br label %for.cond
178+
179+
; Per SPIR-V spec, LoopControlPipelineEnableINTEL = 0x80000 (524288)
180+
; CHECK-SPIRV: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 524288 1
181+
; CHECK-SPIRV-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
182+
; CHECK-SPIRV-NEGATIVE-NOT: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 524288 1
183+
for.cond: ; preds = %for.inc, %entry
184+
%0 = load i32, i32* %i, align 4
185+
%cmp = icmp ne i32 %0, 10
186+
br i1 %cmp, label %for.body, label %for.end
187+
188+
for.body: ; preds = %for.cond
189+
%1 = load i32, i32* %i, align 4
190+
%idxprom = sext i32 %1 to i64
191+
%arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* %a, i64 0, i64 %idxprom
192+
store i32 0, i32* %arrayidx, align 4
193+
br label %for.inc
194+
195+
for.inc: ; preds = %for.body
196+
%2 = load i32, i32* %i, align 4
197+
%inc = add nsw i32 %2, 1
198+
store i32 %inc, i32* %i, align 4
199+
br label %for.cond, !llvm.loop !12
200+
201+
for.end: ; preds = %for.cond
202+
ret void
203+
}
204+
205+
; Function Attrs: noinline nounwind optnone
206+
define spir_func void @loop_coalesce() #0 {
207+
entry:
208+
%i = alloca i32, align 4
209+
%m = alloca i32, align 4
210+
store i32 0, i32* %i, align 4
211+
store i32 42, i32* %m, align 4
212+
br label %while.cond
213+
214+
; Per SPIR-V spec, LoopControlLoopCoalesceINTEL = 0x100000 (1048576)
215+
; CHECK-SPIRV: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 1048576 4
216+
; CHECK-SPIRV-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
217+
; CHECK-SPIRV-NEGATIVE-NOT: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 1048576 4
218+
while.cond: ; preds = %if.end, %if.then, %entry
219+
%0 = load i32, i32* %i, align 4
220+
%1 = load i32, i32* %m, align 4
221+
%cmp = icmp slt i32 %0, %1
222+
br i1 %cmp, label %while.body, label %while.end
223+
224+
while.body: ; preds = %while.cond
225+
%2 = load i32, i32* %i, align 4
226+
%rem = srem i32 %2, 2
227+
%tobool = icmp ne i32 %rem, 0
228+
br i1 %tobool, label %if.then, label %if.end
229+
230+
if.then: ; preds = %while.body
231+
%3 = load i32, i32* %i, align 4
232+
%inc = add nsw i32 %3, 1
233+
store i32 %inc, i32* %i, align 4
234+
br label %while.cond, !llvm.loop !14
235+
236+
if.end: ; preds = %while.body
237+
br label %while.cond, !llvm.loop !14
238+
239+
while.end: ; preds = %while.cond
240+
store i32 0, i32* %i, align 4
241+
br label %while.cond1
242+
243+
; Per SPIR-V spec, LoopControlLoopCoalesceINTEL = 0x100000 (1048576)
244+
; CHECK-SPIRV: 4 LoopMerge {{[0-9]+}} {{[0-9]+}} 1048576
245+
; CHECK-SPIRV-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
246+
; CHECK-SPIRV-NEGATIVE-NOT: 4 LoopMerge {{[0-9]+}} {{[0-9]+}} 1048576
247+
while.cond1: ; preds = %if.end8, %if.then6, %while.end
248+
%4 = load i32, i32* %i, align 4
249+
%5 = load i32, i32* %m, align 4
250+
%cmp2 = icmp slt i32 %4, %5
251+
br i1 %cmp2, label %while.body3, label %while.end9
252+
253+
while.body3: ; preds = %while.cond1
254+
%6 = load i32, i32* %i, align 4
255+
%rem4 = srem i32 %6, 3
256+
%tobool5 = icmp ne i32 %rem4, 0
257+
br i1 %tobool5, label %if.then6, label %if.end8
258+
259+
if.then6: ; preds = %while.body3
260+
%7 = load i32, i32* %i, align 4
261+
%inc7 = add nsw i32 %7, 1
262+
store i32 %inc7, i32* %i, align 4
263+
br label %while.cond1, !llvm.loop !16
264+
265+
if.end8: ; preds = %while.body3
266+
br label %while.cond1, !llvm.loop !16
267+
268+
while.end9: ; preds = %while.cond1
269+
ret void
270+
}
271+
272+
; Function Attrs: noinline nounwind optnone
273+
define spir_func void @max_interleaving() #0 {
274+
entry:
275+
%a = alloca [10 x i32], align 4
276+
%i = alloca i32, align 4
277+
store i32 0, i32* %i, align 4
278+
br label %for.cond
279+
280+
; Per SPIR-V spec, LoopControlMaxInterleavingINTEL = 0x200000 (2097152)
281+
; CHECK-SPIRV: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 2097152 3
282+
; CHECK-SPIRV-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
283+
; CHECK-SPIRV-NEGATIVE-NOT: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 2097152 3
284+
for.cond: ; preds = %for.inc, %entry
285+
%0 = load i32, i32* %i, align 4
286+
%cmp = icmp ne i32 %0, 10
287+
br i1 %cmp, label %for.body, label %for.end
288+
289+
for.body: ; preds = %for.cond
290+
%1 = load i32, i32* %i, align 4
291+
%idxprom = sext i32 %1 to i64
292+
%arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* %a, i64 0, i64 %idxprom
293+
store i32 0, i32* %arrayidx, align 4
294+
br label %for.inc
295+
296+
for.inc: ; preds = %for.body
297+
%2 = load i32, i32* %i, align 4
298+
%inc = add nsw i32 %2, 1
299+
store i32 %inc, i32* %i, align 4
300+
br label %for.cond, !llvm.loop !18
301+
302+
for.end: ; preds = %for.cond
303+
ret void
304+
}
305+
306+
; Function Attrs: noinline nounwind optnone
307+
define spir_func void @speculated_iterations() #0 {
308+
entry:
309+
%a = alloca [10 x i32], align 4
310+
%i = alloca i32, align 4
311+
store i32 0, i32* %i, align 4
312+
br label %for.cond
313+
314+
; Per SPIR-V spec, LoopControlSpeculatedIterationsINTEL = 0x400000 (4194304)
315+
; CHECK-SPIRV: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 4194304 4
316+
; CHECK-SPIRV-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
317+
; CHECK-SPIRV-NEGATIVE-NOT: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 4194304 4
318+
for.cond: ; preds = %for.inc, %entry
319+
%0 = load i32, i32* %i, align 4
320+
%cmp = icmp ne i32 %0, 10
321+
br i1 %cmp, label %for.body, label %for.end
322+
323+
for.body: ; preds = %for.cond
324+
%1 = load i32, i32* %i, align 4
325+
%idxprom = sext i32 %1 to i64
326+
%arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* %a, i64 0, i64 %idxprom
327+
store i32 0, i32* %arrayidx, align 4
328+
br label %for.inc
329+
330+
for.inc: ; preds = %for.body
331+
%2 = load i32, i32* %i, align 4
332+
%inc = add nsw i32 %2, 1
333+
store i32 %inc, i32* %i, align 4
334+
br label %for.cond, !llvm.loop !20
335+
336+
for.end: ; preds = %for.cond
337+
ret void
338+
}
339+
171340
attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
172341

173342
!llvm.module.flags = !{!0}
@@ -186,18 +355,38 @@ attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide
186355
!9 = distinct !{!9, !10}
187356
!10 = !{!"llvm.loop.max_concurrency.count", i32 2}
188357
!11 = distinct !{!11, !8, !10}
358+
!12 = distinct !{!12, !13}
359+
!13 = !{!"llvm.loop.intel.pipelining.enable", i32 1}
360+
!14 = distinct !{!14, !15}
361+
!15 = !{!"llvm.loop.coalesce.count", i32 4}
362+
!16 = distinct !{!16, !17}
363+
!17 = !{!"llvm.loop.coalesce.enable"}
364+
!18 = distinct !{!18, !19}
365+
!19 = !{!"llvm.loop.max_interleaving.count", i32 3}
366+
!20 = distinct !{!20, !21}
367+
!21 = !{!"llvm.loop.intel.speculated.iterations.count", i32 4}
189368

190369
; CHECK-LLVM: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_A:[0-9]+]]
191370
; CHECK-LLVM: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_B:[0-9]+]]
192371
; CHECK-LLVM: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_C:[0-9]+]]
193372
; CHECK-LLVM: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_D:[0-9]+]]
194373
; CHECK-LLVM: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_E:[0-9]+]]
374+
; CHECK-LLVM: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_F:[0-9]+]]
375+
; CHECK-LLVM: br label %while.cond{{[0-9]*}}, !llvm.loop ![[MD_G:[0-9]+]]
376+
; CHECK-LLVM: br label %while.cond{{[0-9]+}}, !llvm.loop ![[MD_H:[0-9]+]]
377+
; CHECK-LLVM: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_I:[0-9]+]]
378+
; CHECK-LLVM: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_J:[0-9]+]]
195379

196380
; CHECK-LLVM-NEGATIVE: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_A:[0-9]+]]
197381
; CHECK-LLVM-NEGATIVE: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_B:[0-9]+]]
198382
; CHECK-LLVM-NEGATIVE-NOT: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_C:[0-9]+]]
199383
; CHECK-LLVM-NEGATIVE-NOT: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_D:[0-9]+]]
200384
; CHECK-LLVM-NEGATIVE-NOT: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_E:[0-9]+]]
385+
; CHECK-LLVM-NEGATIVE-NOT: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_F:[0-9]+]]
386+
; CHECK-LLVM-NEGATIVE-NOT: br label %while.cond{{[0-9]*}}, !llvm.loop ![[MD_G:[0-9]+]]
387+
; CHECK-LLVM-NEGATIVE-NOT: br label %while.cond{{[0-9]+}}, !llvm.loop ![[MD_H:[0-9]+]]
388+
; CHECK-LLVM-NEGATIVE-NOT: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_I:[0-9]+]]
389+
; CHECK-LLVM-NEGATIVE-NOT: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_J:[0-9]+]]
201390

202391
; CHECK-LLVM: ![[MD_A]] = distinct !{![[MD_A]], ![[MD_ivdep_enable:[0-9]+]]}
203392
; CHECK-LLVM: ![[MD_ivdep_enable]] = !{!"llvm.loop.ivdep.enable"}
@@ -208,6 +397,17 @@ attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide
208397
; CHECK-LLVM: ![[MD_D]] = distinct !{![[MD_D]], ![[MD_max_concurrency:[0-9]+]]}
209398
; CHECK-LLVM: ![[MD_max_concurrency]] = !{!"llvm.loop.max_concurrency.count", i32 2}
210399
; CHECK-LLVM: ![[MD_E]] = distinct !{![[MD_E]], ![[MD_ii:[0-9]+]], ![[MD_max_concurrency:[0-9]+]]}
400+
; CHECK-LLVM: ![[MD_F]] = distinct !{![[MD_F]], ![[MD_pipelining:[0-9]+]]}
401+
; CHECK-LLVM: ![[MD_pipelining]] = !{!"llvm.loop.intel.pipelining.enable", i32 1}
402+
; CHECK-LLVM: ![[MD_G]] = distinct !{![[MD_G]], ![[MD_loop_coalesce_count:[0-9]+]]}
403+
; CHECK-LLVM: ![[MD_loop_coalesce_count]] = !{!"llvm.loop.coalesce.count", i32 4}
404+
; CHECK-LLVM: ![[MD_H]] = distinct !{![[MD_H]], ![[MD_loop_coalesce:[0-9]+]]}
405+
; CHECK-LLVM: ![[MD_loop_coalesce]] = !{![[MD_loop_coalesce_enable:[0-9]+]]}
406+
; CHECK-LLVM: ![[MD_loop_coalesce_enable]] = !{!"llvm.loop.coalesce.enable"}
407+
; CHECK-LLVM: ![[MD_I]] = distinct !{![[MD_I]], ![[MD_max_interleaving:[0-9]+]]}
408+
; CHECK-LLVM: ![[MD_max_interleaving]] = !{!"llvm.loop.max_interleaving.count", i32 3}
409+
; CHECK-LLVM: ![[MD_J]] = distinct !{![[MD_J]], ![[MD_spec_iterations:[0-9]+]]}
410+
; CHECK-LLVM: ![[MD_spec_iterations]] = !{!"llvm.loop.intel.speculated.iterations.count", i32 4}
211411

212412
; CHECK-LLVM-NEGATIVE: ![[MD_A]] = distinct !{![[MD_A]], ![[MD_ivdep_enable:[0-9]+]]}
213413
; CHECK-LLVM-NEGATIVE: ![[MD_ivdep_enable]] = !{!"llvm.loop.ivdep.enable"}
@@ -218,3 +418,14 @@ attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide
218418
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_D]] = distinct !{![[MD_D]], ![[MD_max_concurrency:[0-9]+]]}
219419
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_max_concurrency]] = !{!"llvm.loop.max_concurrency.count", i32 2}
220420
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_E]] = distinct !{![[MD_E]], ![[MD_ii:[0-9]+]], ![[MD_max_concurrency:[0-9]+]]}
421+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_F]] = distinct !{![[MD_F]], ![[MD_pipelining:[0-9]+]]}
422+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_pipelining]] = !{!"llvm.loop.intel.pipelining.enable", i32 1}
423+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_G]] = distinct !{![[MD_G]], ![[MD_loop_coalesce_count:[0-9]+]]}
424+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_loop_coalesce_count]] = !{!"llvm.loop.coalesce.count", i32 4}
425+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_H]] = distinct !{![[MD_H]], ![[MD_loop_coalesce:[0-9]+]]}
426+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_loop_coalesce]] = !{![[MD_loop_coalesce_enable:[0-9]+]]}
427+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_loop_coalesce_enable]] = !{!"llvm.loop.coalesce.enable"}
428+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_I]] = distinct !{![[MD_I]], ![[MD_max_interleaving:[0-9]+]]}
429+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_max_interleaving]] = !{!"llvm.loop.max_interleaving.count", i32 3}
430+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_J]] = distinct !{![[MD_J]], ![[MD_spec_iterations:[0-9]+]]}
431+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_spec_iterations]] = !{!"llvm.loop.intel.speculated.iterations.count", i32 4}

0 commit comments

Comments
 (0)