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DenisBakhvalovDenisBakhvalov
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[Driver] Pass optimization options to sycl-post-link (#3207)
This is one of the patches for moving ESIMD passes from clang FE (BackendUtils.cpp) to sycl-post-link. This patch is a continuation for #3195 and it passes the optimization level to the sycl-post-link.
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‎clang/lib/Driver/ToolChains/Clang.cpp

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@@ -8269,6 +8269,32 @@ static void addArgs(ArgStringList &DstArgs, const llvm::opt::ArgList &Alloc,
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}
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}
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// Partially copied from clang/lib/Frontend/CompilerInvocation.cpp
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static std::string getSYCLPostLinkOptimizationLevel(const ArgList &Args) {
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if (Arg *A = Args.getLastArg(options::OPT_O_Group)) {
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if (A->getOption().matches(options::OPT_O0))
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return "-O0";
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if (A->getOption().matches(options::OPT_Ofast))
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return "-O3";
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assert(A->getOption().matches(options::OPT_O));
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StringRef S(A->getValue());
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if (S == "g")
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return "-O1";
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// Options -O[1|2|3|s|z] are passed as they are. '-O0' is handled earlier.
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std::array<char, 5> AcceptedOptions = {'1', '2', '3', 's', 'z'};
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if (std::any_of(AcceptedOptions.begin(), AcceptedOptions.end(),
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[=](char c) { return c == S[0]; }))
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return std::string("-O") + S[0];
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}
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// The default for SYCL device code optimization
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return "-O2";
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}
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// sycl-post-link tool normally outputs a file table (see the tool sources for
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// format description) which lists all the other output files associated with
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// the device LLVMIR bitcode. This is basically a triple of bitcode, symbols
@@ -8325,6 +8351,8 @@ void SYCLPostLink::ConstructJob(Compilation &C, const JobAction &JA,
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options::OPT_fno_sycl_device_code_lower_esimd, false))
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addArgs(CmdArgs, TCArgs, {"-lower-esimd"});
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}
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addArgs(CmdArgs, TCArgs,
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{StringRef(getSYCLPostLinkOptimizationLevel(TCArgs))});
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// specialization constants processing is mandatory
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auto *SYCLPostLink = llvm::dyn_cast<SYCLPostLinkJobAction>(&JA);
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if (SYCLPostLink && SYCLPostLink->getRTSetsSpecConstants())

‎clang/test/Driver/sycl-device-lib.cpp

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@@ -121,7 +121,7 @@
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// RUN: | FileCheck %s -check-prefix=SYCL_LLVM_LINK_NO_DEVICE_LIB
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// SYCL_LLVM_LINK_NO_DEVICE_LIB: clang{{.*}} "-cc1" {{.*}} "-fsycl-is-device"
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// SYCL_LLVM_LINK_NO_DEVICE_LIB-NOT: llvm-link{{.*}} "-only-needed"
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// SYCL_LLVM_LINK_NO_DEVICE_LIB: sycl-post-link{{.*}} "-symbols" "-split-esimd" "-spec-const=rt" "-o" "{{.*}}.table" "{{.*}}.bc"
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// SYCL_LLVM_LINK_NO_DEVICE_LIB: sycl-post-link{{.*}} "-symbols" "-split-esimd" "-O2" "-spec-const=rt" "-o" "{{.*}}.table" "{{.*}}.bc"
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/// ###########################################################################
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/// test llvm-link behavior for special user input whose filename resembles SYCL device library

‎clang/test/Driver/sycl-intelfpga-aoco-win.cpp

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@@ -47,7 +47,7 @@
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// CHK-FPGA-AOCO: llvm-link{{.*}} "[[OUTLIB]]" "-o" "[[LINKEDBC:.+\.bc]]"
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// CHK-FPGA-AOCO: sycl-post-link
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// CHK-FPGA-AOCO-NOT: -split-esimd
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// CHK-FPGA-AOCO: "-ir-output-only" "-spec-const=default" "-o" "[[PLINKEDBC:.+\.bc]]" "[[LINKEDBC]]"
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// CHK-FPGA-AOCO: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[PLINKEDBC:.+\.bc]]" "[[LINKEDBC]]"
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// CHK-FPGA-AOCO: llvm-spirv{{.*}} "-o" "[[TARGSPV:.+\.spv]]" {{.*}} "[[PLINKEDBC]]"
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// CHK-FPGA-AOCO: clang-offload-bundler{{.*}} "-type=aoo" "-targets=sycl-fpga_aoco-intel-unknown-sycldevice" "-inputs=[[INPUTLIB]]" "-outputs=[[AOCOLIST:.+\.txt]]" "-unbundle"
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// CHK-FPGA-AOCO: aoc{{.*}} "-o" "[[AOCXOUT:.+\.aocx]]" "[[TARGSPV]]" "-library-list=[[AOCOLIST]]" "-sycl"

‎clang/test/Driver/sycl-intelfpga-aoco.cpp

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@@ -85,7 +85,7 @@
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// CHK-FPGA-AOCO: llvm-link{{.*}} "[[OUTLIB]]" "-o" "[[LINKEDBC:.+\.bc]]"
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// CHK-FPGA-AOCO: sycl-post-link
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// CHK-FPGA-AOCO-NOT: "-split-esimd"
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// CHK-FPGA-AOCO: "-ir-output-only" "-spec-const=default" "-o" "[[PLINKEDBC:.+\.bc]]" "[[LINKEDBC]]"
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// CHK-FPGA-AOCO: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[PLINKEDBC:.+\.bc]]" "[[LINKEDBC]]"
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// CHK-FPGA-AOCO: llvm-spirv{{.*}} "-o" "[[TARGSPV:.+\.spv]]" {{.*}} "[[PLINKEDBC]]"
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// CHK-FPGA-AOCO: clang-offload-bundler{{.*}} "-type=aoo" "-targets=sycl-fpga_aoco-intel-unknown-sycldevice" "-inputs=[[INPUTLIB]]" "-outputs=[[AOCOLIST:.+\.txt]]" "-unbundle"
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// CHK-FPGA-AOCO: aoc{{.*}} "-o" "[[AOCXOUT:.+\.aocx]]" "[[TARGSPV]]" "-library-list=[[AOCOLIST]]" "-sycl"

‎clang/test/Driver/sycl-offload-intelfpga.cpp

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@@ -33,7 +33,7 @@
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// CHK-FPGA-LINK: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]"
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// CHK-FPGA-LINK: sycl-post-link
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// CHK-FPGA-LINK-NOT: -split-esimd
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// CHK-FPGA-LINK: "-ir-output-only" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]"
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// CHK-FPGA-LINK: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]"
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// CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-debug-info-version=legacy" "-spirv-allow-extra-diexpressions" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2]]"
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// CHK-FPGA-EARLY: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl"
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// CHK-FPGA-IMAGE: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocx]]" "[[OUTPUT3]]" "-sycl"
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// CHK-FPGA-LINK-WIN: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]"
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// CHK-FPGA-LINK-WIN: sycl-post-link
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// CHK-FPGA-LINK-WIN-NOT: -split-esimd
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// CHK-FPGA-LINK-WIN: "-ir-output-only" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]"
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// CHK-FPGA-LINK-WIN: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]"
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// CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-debug-info-version=legacy" "-spirv-allow-extra-diexpressions" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2]]"
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// CHK-FPGA-LINK-WIN: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl"
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// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl"
@@ -132,7 +132,7 @@
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// CHK-FPGA: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_BC:.+\.bc]]"
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// CHK-FPGA: sycl-post-link
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// CHK-FPGA-NOT: -split-esimd
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// CHK-FPGA: "-ir-output-only" "-spec-const=default" "-o" "[[OUTPUT3_BC:.+\.bc]]" "[[OUTPUT2_BC]]"
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// CHK-FPGA: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[OUTPUT3_BC:.+\.bc]]" "[[OUTPUT2_BC]]"
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// CHK-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT5:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-debug-info-version=legacy" "-spirv-allow-extra-diexpressions" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT3_BC]]"
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// CHK-FPGA: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-fpga_dep" {{.*}} "-outputs=[[DEPFILE:.+\.d]]" "-unbundle"
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// CHK-FPGA: aoc{{.*}} "-o" "[[OUTPUT6:.+\.aocx]]" "[[OUTPUT5]]" "-sycl" "-dep-files=[[DEPFILE]]"
@@ -186,7 +186,7 @@
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// CHK-FPGA-AOCX-SRC: llvm-link{{.*}} "[[DEVICEBC]]" "-o" "[[LLVMLINKOUT:.+\.bc]]" "--suppress-warnings"
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// CHK-FPGA-AOCX-SRC: sycl-post-link
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// CHK-FPGA-AOCX-SRC-NOT: -split-esimd
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// CHK-FPGA-AOCX-SRC: "-ir-output-only" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.bc]]" "[[LLVMLINKOUT]]
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// CHK-FPGA-AOCX-SRC: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.bc]]" "[[LLVMLINKOUT]]
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// CHK-FPGA-AOCX-SRC: llvm-spirv{{.*}} "-o" "[[LLVMSPVOUT:.+\.spv]]" {{.*}} "[[POSTLINKOUT]]"
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// CHK-FPGA-AOCX-SRC: aoc{{.*}} "-o" "[[AOCOUT:.+\.aocx]]" "[[LLVMSPVOUT]]" "-sycl"
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// CHK-FPGA-AOCX-SRC: clang-offload-wrapper{{.*}} "-o=[[WRAPOUTSRC:.+.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "[[AOCOUT]]"
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// CHK-FPGA-AOCX-OBJ: llvm-link{{.*}} "[[DEVICEOBJ]]" "-o" "[[LLVMLINKOUT:.+\.bc]]" "--suppress-warnings"
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// CHK-FPGA-AOCX-OBJ: sycl-post-link
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// CHK-FPGA-AOCX-OBJ-NOT: -split-esimd
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// CHK-FPGA-AOCX-OBJ: "-ir-output-only" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.bc]]" "[[LLVMLINKOUT]]
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// CHK-FPGA-AOCX-OBJ: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.bc]]" "[[LLVMLINKOUT]]
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// CHK-FPGA-AOCX-OBJ: llvm-spirv{{.*}} "-o" "[[LLVMSPVOUT:.+\.spv]]" {{.*}} "[[POSTLINKOUT]]"
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// CHK-FPGA-AOCX-OBJ: aoc{{.*}} "-o" "[[AOCOUT:.+\.aocx]]" "[[LLVMSPVOUT]]" "-sycl"
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// CHK-FPGA-AOCX-OBJ: clang-offload-wrapper{{.*}} "-o=[[WRAPOUTSRC:.+.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "[[AOCOUT]]"

‎clang/test/Driver/sycl-offload.c

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@@ -903,3 +903,33 @@
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// CHECK-STD-OVR: clang{{.*}} "-fsyntax-only" {{.*}} "-std=c++14"
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// CHECK-STD-OVR: clang{{.*}} "-emit-obj" {{.*}} "-std=c++14"
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// CHECK-STD-OVR-NOT: clang{{.*}} "-std=c++17"
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// Check sycl-post-link optimization level.
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// Default is O2
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// RUN: %clang -### -fsycl %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O2
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// RUN: %clang_cl -### -fsycl %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O2
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// Common options for %clang and %clang_cl
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// RUN: %clang -### -fsycl -O1 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O1
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// RUN: %clang_cl -### -fsycl /O1 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-Os
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// RUN: %clang -### -fsycl -O2 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O2
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// RUN: %clang_cl -### -fsycl /O2 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O2
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// RUN: %clang -### -fsycl -Os %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-Os
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// RUN: %clang_cl -### -fsycl /Os %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-Os
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// %clang options
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// RUN: %clang -### -fsycl -O0 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O0
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// RUN: %clang -### -fsycl -Ofast %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O3
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// RUN: %clang -### -fsycl -O3 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O3
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// RUN: %clang -### -fsycl -Oz %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-Oz
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// RUN: %clang -### -fsycl -Og %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O1
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// %clang_cl options
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// RUN: %clang_cl -### -fsycl /Od %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O0
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// RUN: %clang_cl -### -fsycl /Ot %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O2
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// only the last option is considered
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// RUN: %clang -### -fsycl -O2 -O1 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-O1
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// RUN: %clang_cl -### -fsycl /O2 /O1 %s 2>&1 | FileCheck %s -check-prefixes=CHK-POST-LINK-OPT-LEVEL-Os
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// CHK-POST-LINK-OPT-LEVEL-O0: sycl-post-link{{.*}} "-O0"
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// CHK-POST-LINK-OPT-LEVEL-O1: sycl-post-link{{.*}} "-O1"
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// CHK-POST-LINK-OPT-LEVEL-O2: sycl-post-link{{.*}} "-O2"
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// CHK-POST-LINK-OPT-LEVEL-O3: sycl-post-link{{.*}} "-O3"
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// CHK-POST-LINK-OPT-LEVEL-Os: sycl-post-link{{.*}} "-Os"
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// CHK-POST-LINK-OPT-LEVEL-Oz: sycl-post-link{{.*}} "-Oz"

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