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AaronBallmanAaronBallman
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Merge remote-tracking branch 'upstream/sycl' into host-device-attr-langopts
2 parents d4994cb + 4ad9e79 commit 95ee4e6

27 files changed

+285
-138
lines changed

‎buildbot/dependency.conf

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@ ocl_cpu_rt_ver=2020.11.11.0.04
44
# https://github.com/intel/llvm/releases/download/2020-WW45/win-oclcpuexp-2020.11.11.0.04_rel.zip
55
ocl_cpu_rt_ver_win=2020.11.11.0.04
66
# Same GPU driver supports Level Zero and OpenCL
7-
# https://github.com/intel/compute-runtime/releases/tag/21.04.18912
8-
ocl_gpu_rt_ver=21.04.18912
7+
# https://github.com/intel/compute-runtime/releases/tag/21.07.19042
8+
ocl_gpu_rt_ver=21.07.19042
99
# Same GPU driver supports Level Zero and OpenCL
1010
# https://downloadmirror.intel.com/30148/a08/igfx_win10_100.9168.zip
1111
ocl_gpu_rt_ver_win=27.20.100.9168
@@ -30,7 +30,7 @@ ocloc_ver_win=27.20.100.9168
3030
[DRIVER VERSIONS]
3131
cpu_driver_lin=2020.11.11.0.04
3232
cpu_driver_win=2020.11.11.0.04
33-
gpu_driver_lin=21.04.18912
33+
gpu_driver_lin=21.07.19042
3434
gpu_driver_win=27.20.100.9168
3535
fpga_driver_lin=2020.11.11.0.04
3636
fpga_driver_win=2020.11.11.0.04

‎buildbot/dependency.py

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,12 +49,18 @@ def do_dependency(args):
4949
# fetch OpenCL headers
5050
ocl_header_dir = os.path.join(args.obj_dir, "OpenCL-Headers")
5151
if not os.path.isdir(ocl_header_dir):
52-
clone_cmd = ["git", "clone", "https://github.com/KhronosGroup/OpenCL-Headers", "OpenCL-Headers"]
52+
clone_cmd = ["git", "clone", "https://github.com/KhronosGroup/OpenCL-Headers",
53+
"OpenCL-Headers", "-b", "v2020.06.16"]
5354
subprocess.check_call(clone_cmd, cwd=args.obj_dir)
5455
else:
5556
fetch_cmd = ["git", "pull", "--ff", "--ff-only", "origin"]
5657
subprocess.check_call(fetch_cmd, cwd=ocl_header_dir)
5758

59+
# Workaround to unblock CI until KhronosGroup/OpenCL-ICD-Loader/pull/124
60+
# is submitted
61+
checkout_cmd = ["git", "checkout", "d1b936b72b9610626ecab8a991cec18348fba047"]
62+
subprocess.check_call(checkout_cmd, cwd=ocl_header_dir)
63+
5864
# fetch and build OpenCL ICD loader
5965
icd_loader_dir = os.path.join(args.obj_dir, "OpenCL-ICD-Loader")
6066
if not os.path.isdir(icd_loader_dir):

‎clang/include/clang/Basic/Attr.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1398,7 +1398,7 @@ def IntelReqdSubGroupSize: InheritableAttr {
13981398
let Spellings = [GNU<"intel_reqd_sub_group_size">,
13991399
CXX11<"intel", "reqd_sub_group_size">];
14001400
let Args = [ExprArgument<"Value">];
1401-
let Subjects = SubjectList<[Function, CXXMethod], ErrorDiag>;
1401+
let Subjects = SubjectList<[Function], ErrorDiag>;
14021402
let Documentation = [IntelReqdSubGroupSizeDocs];
14031403
let LangOpts = [OpenCL, SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
14041404
}

‎clang/include/clang/Sema/Sema.h

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10210,6 +10210,16 @@ class Sema final {
1021010210
template <typename AttrType>
1021110211
void addIntelTripleArgAttr(Decl *D, const AttributeCommonInfo &CI,
1021210212
Expr *XDimExpr, Expr *YDimExpr, Expr *ZDimExpr);
10213+
void AddIntelReqdSubGroupSize(Decl *D, const AttributeCommonInfo &CI,
10214+
Expr *E);
10215+
IntelReqdSubGroupSizeAttr *
10216+
MergeIntelReqdSubGroupSizeAttr(Decl *D, const IntelReqdSubGroupSizeAttr &A);
10217+
void AddSYCLIntelNumSimdWorkItemsAttr(Decl *D, const AttributeCommonInfo &CI,
10218+
Expr *E);
10219+
SYCLIntelNumSimdWorkItemsAttr *
10220+
MergeSYCLIntelNumSimdWorkItemsAttr(Decl *D,
10221+
const SYCLIntelNumSimdWorkItemsAttr &A);
10222+
1021310223
/// AddAlignedAttr - Adds an aligned attribute to a particular declaration.
1021410224
void AddAlignedAttr(Decl *D, const AttributeCommonInfo &CI, Expr *E,
1021510225
bool IsPackExpansion);
@@ -13068,16 +13078,14 @@ void Sema::addIntelSingleArgAttr(Decl *D, const AttributeCommonInfo &CI,
1306813078
return;
1306913079
E = ICE.get();
1307013080
int32_t ArgInt = ArgVal.getSExtValue();
13071-
if (CI.getParsedKind() == ParsedAttr::AT_IntelReqdSubGroupSize ||
13072-
CI.getParsedKind() == ParsedAttr::AT_IntelFPGAMaxReplicates) {
13081+
if (CI.getParsedKind() == ParsedAttr::AT_IntelFPGAMaxReplicates) {
1307313082
if (ArgInt <= 0) {
1307413083
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
1307513084
<< CI << /*positive*/ 0;
1307613085
return;
1307713086
}
1307813087
}
13079-
if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim ||
13080-
CI.getParsedKind() == ParsedAttr::AT_SYCLIntelNumSimdWorkItems) {
13088+
if (CI.getParsedKind() == ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim) {
1308113089
if (ArgInt < 0) {
1308213090
Diag(E->getExprLoc(), diag::err_attribute_requires_positive_integer)
1308313091
<< CI << /*non-negative*/ 1;

‎clang/lib/CodeGen/BackendUtil.cpp

Lines changed: 0 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,6 @@
2828
#include "llvm/CodeGen/RegAllocRegistry.h"
2929
#include "llvm/CodeGen/SchedulerRegistry.h"
3030
#include "llvm/CodeGen/TargetSubtargetInfo.h"
31-
#include "llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h"
3231
#include "llvm/IR/DataLayout.h"
3332
#include "llvm/IR/IRPrintingPasses.h"
3433
#include "llvm/IR/LegacyPassManager.h"
@@ -42,7 +41,6 @@
4241
#include "llvm/Passes/PassBuilder.h"
4342
#include "llvm/Passes/PassPlugin.h"
4443
#include "llvm/Passes/StandardInstrumentations.h"
45-
#include "llvm/SYCLLowerIR/LowerESIMD.h"
4644
#include "llvm/Support/BuryPointer.h"
4745
#include "llvm/Support/CommandLine.h"
4846
#include "llvm/Support/MemoryBuffer.h"
@@ -839,25 +837,6 @@ void EmitAssemblyHelper::CreatePasses(legacy::PassManager &MPM,
839837

840838
PMBuilder.populateFunctionPassManager(FPM);
841839
PMBuilder.populateModulePassManager(MPM);
842-
843-
// Customize the tail of the module passes list for the ESIMD extension.
844-
if (LangOpts.SYCLIsDevice && LangOpts.SYCLExplicitSIMD &&
845-
CodeGenOpts.OptimizationLevel != 0) {
846-
MPM.add(createESIMDLowerVecArgPass());
847-
MPM.add(createESIMDLowerLoadStorePass());
848-
MPM.add(createSROAPass());
849-
MPM.add(createEarlyCSEPass(true));
850-
MPM.add(createInstructionCombiningPass());
851-
MPM.add(createDeadCodeEliminationPass());
852-
MPM.add(createFunctionInliningPass(
853-
CodeGenOpts.OptimizationLevel, CodeGenOpts.OptimizeSize,
854-
(!CodeGenOpts.SampleProfileFile.empty() &&
855-
CodeGenOpts.PrepareForThinLTO)));
856-
MPM.add(createSROAPass());
857-
MPM.add(createEarlyCSEPass(true));
858-
MPM.add(createInstructionCombiningPass());
859-
MPM.add(createDeadCodeEliminationPass());
860-
}
861840
}
862841

863842
static void setCommandLineOpts(const CodeGenOptions &CodeGenOpts) {
@@ -954,11 +933,6 @@ void EmitAssemblyHelper::EmitAssembly(BackendAction Action,
954933
PerFunctionPasses.add(
955934
createTargetTransformInfoWrapperPass(getTargetIRAnalysis()));
956935

957-
// ESIMD extension always requires lowering of certain IR constructs, such as
958-
// ESIMD C++ intrinsics, as the last FE step.
959-
if (LangOpts.SYCLIsDevice && LangOpts.SYCLExplicitSIMD)
960-
PerModulePasses.add(createSYCLLowerESIMDPass());
961-
962936
CreatePasses(PerModulePasses, PerFunctionPasses);
963937

964938
legacy::PassManager CodeGenPasses;
@@ -976,9 +950,6 @@ void EmitAssemblyHelper::EmitAssembly(BackendAction Action,
976950
!LangOpts.SYCLExplicitSIMD && LangOpts.EnableDAEInSpirKernels)
977951
PerModulePasses.add(createDeadArgEliminationSYCLPass());
978952

979-
if (LangOpts.SYCLIsDevice && LangOpts.SYCLExplicitSIMD)
980-
PerModulePasses.add(createGenXSPIRVWriterAdaptorPass());
981-
982953
switch (Action) {
983954
case Backend_EmitNothing:
984955
break;

‎clang/lib/CodeGen/CMakeLists.txt

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -27,14 +27,6 @@ set(LLVM_LINK_COMPONENTS
2727
TransformUtils
2828
)
2929

30-
31-
get_property(LLVMGenXIntrinsics_SOURCE_DIR GLOBAL PROPERTY LLVMGenXIntrinsics_SOURCE_PROP)
32-
get_property(LLVMGenXIntrinsics_BINARY_DIR GLOBAL PROPERTY LLVMGenXIntrinsics_BINARY_PROP)
33-
34-
include_directories(
35-
${LLVMGenXIntrinsics_SOURCE_DIR}/GenXIntrinsics/include
36-
${LLVMGenXIntrinsics_BINARY_DIR}/GenXIntrinsics/include)
37-
3830
add_clang_library(clangCodeGen
3931
BackendUtil.cpp
4032
CGAtomic.cpp
@@ -96,14 +88,9 @@ add_clang_library(clangCodeGen
9688
TargetInfo.cpp
9789
VarBypassDetector.cpp
9890

99-
ADDITIONAL_HEADER_DIRS
100-
${LLVMGenXIntrinsics_SOURCE_DIR}/GenXIntrinsics/include
101-
${LLVMGenXIntrinsics_BINARY_DIR}/GenXIntrinsics/include
102-
10391
DEPENDS
10492
${codegen_deps}
10593
intrinsics_gen
106-
LLVMGenXIntrinsics
10794

10895
LINK_LIBS
10996
clangAnalysis
@@ -112,5 +99,4 @@ add_clang_library(clangCodeGen
11299
clangFrontend
113100
clangLex
114101
clangSerialization
115-
LLVMGenXIntrinsics
116102
)

‎clang/lib/CodeGen/CodeGenModule.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1656,7 +1656,9 @@ void CodeGenModule::GenOpenCLArgMetadata(llvm::Function *Fn,
16561656
CGF->Builder.getInt1(parm->hasAttr<SYCLSimdAccessorPtrAttr>())));
16571657
}
16581658

1659-
if (LangOpts.SYCLIsDevice && !LangOpts.SYCLExplicitSIMD)
1659+
bool IsEsimdFunction = FD && FD->hasAttr<SYCLSimdAttr>();
1660+
1661+
if (LangOpts.SYCLIsDevice && !IsEsimdFunction)
16601662
Fn->setMetadata("kernel_arg_buffer_location",
16611663
llvm::MDNode::get(VMContext, argSYCLBufferLocationAttr));
16621664
else {
@@ -1670,7 +1672,7 @@ void CodeGenModule::GenOpenCLArgMetadata(llvm::Function *Fn,
16701672
llvm::MDNode::get(VMContext, argBaseTypeNames));
16711673
Fn->setMetadata("kernel_arg_type_qual",
16721674
llvm::MDNode::get(VMContext, argTypeQuals));
1673-
if (FD && FD->hasAttr<SYCLSimdAttr>())
1675+
if (IsEsimdFunction)
16741676
Fn->setMetadata("kernel_arg_accessor_ptr",
16751677
llvm::MDNode::get(VMContext, argESIMDAccPtrs));
16761678
if (getCodeGenOpts().EmitOpenCLArgMetadata)

‎clang/lib/Driver/ToolChains/Clang.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8348,7 +8348,7 @@ void SYCLPostLink::ConstructJob(Compilation &C, const JobAction &JA,
83488348
options::OPT_fno_sycl_device_code_split_esimd, true))
83498349
addArgs(CmdArgs, TCArgs, {"-split-esimd"});
83508350
if (TCArgs.hasFlag(options::OPT_fsycl_device_code_lower_esimd,
8351-
options::OPT_fno_sycl_device_code_lower_esimd, false))
8351+
options::OPT_fno_sycl_device_code_lower_esimd, true))
83528352
addArgs(CmdArgs, TCArgs, {"-lower-esimd"});
83538353
}
83548354
addArgs(CmdArgs, TCArgs,

‎clang/lib/Sema/SemaDecl.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2618,6 +2618,10 @@ static bool mergeDeclAttribute(Sema &S, NamedDecl *D,
26182618
NewAttr = S.mergeEnforceTCBAttr(D, *TCBA);
26192619
else if (const auto *TCBLA = dyn_cast<EnforceTCBLeafAttr>(Attr))
26202620
NewAttr = S.mergeEnforceTCBLeafAttr(D, *TCBLA);
2621+
else if (const auto *A = dyn_cast<IntelReqdSubGroupSizeAttr>(Attr))
2622+
NewAttr = S.MergeIntelReqdSubGroupSizeAttr(D, *A);
2623+
else if (const auto *A = dyn_cast<SYCLIntelNumSimdWorkItemsAttr>(Attr))
2624+
NewAttr = S.MergeSYCLIntelNumSimdWorkItemsAttr(D, *A);
26212625
else if (Attr->shouldInheritEvenIfAlreadyPresent() || !DeclHasAttr(D, Attr))
26222626
NewAttr = cast<InheritableAttr>(Attr->clone(S.Context));
26232627

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