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[Opaque pointer] Port tests in AMDGPU/NVPTX/SYCL-FUSION etc to opaque pointers (#10889)
This is in preparation of -DINTEL_SYCL_OPAQUEPOINTER_READY=1 - Port barrier_intrinsic.ll to opaque pointer - Port spirv-to-ir-wrapper.ll to opaque pointers - Update NVPTX tests to opaque pointers - Update AMDGPU tests to opaque pointers - Update sycl fusion tests to opaque pointers
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37 files changed

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-858
lines changed

37 files changed

+835
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lines changed

‎llvm/test/Analysis/GlobalsModRef/barrier_intrinsic.ll

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -8,21 +8,21 @@ target triple = "nvptx"
88

99
@foo.l.0 = internal unnamed_addr addrspace(3) global i32 undef, align 4
1010

11-
define dso_local spir_kernel void @foo(i32 addrspace(1)* nocapture %0) {
11+
define dso_local spir_kernel void @foo(ptr addrspace(1) nocapture %0) {
1212
; CHECK-LABEL: @foo(
1313
; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @_Z13get_global_idj(i32 0) #0
1414
; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @_Z12get_local_idj(i32 0) #0
1515
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
1616
; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP7:%.*]]
1717
; CHECK: 5:
1818
; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP2]], 5
19-
; CHECK-NEXT: store i32 [[TMP6]], i32 addrspace(3)* @foo.l.0, align 4
19+
; CHECK-NEXT: store i32 [[TMP6]], ptr addrspace(3) @foo.l.0, align 4
2020
; CHECK-NEXT: br label [[TMP7]]
2121
; CHECK: 7:
2222
; CHECK-NEXT: tail call void @llvm.nvvm.barrier0() #2
23-
; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32 addrspace(3)* @foo.l.0, align 4
24-
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[TMP0:%.*]], i32 [[TMP2]]
25-
; CHECK-NEXT: store i32 [[TMP8]], i32 addrspace(1)* [[TMP9]], align 4
23+
; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(3) @foo.l.0, align 4
24+
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[TMP0:%.*]], i32 [[TMP2]]
25+
; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) [[TMP9]], align 4
2626
; CHECK-NEXT: ret void
2727
;
2828
%2 = tail call i32 @_Z13get_global_idj(i32 0) #0
@@ -32,14 +32,14 @@ define dso_local spir_kernel void @foo(i32 addrspace(1)* nocapture %0) {
3232

3333
5: ; preds = %1
3434
%6 = add i32 %2, 5
35-
store i32 %6, i32 addrspace(3)* @foo.l.0, align 4
35+
store i32 %6, ptr addrspace(3) @foo.l.0, align 4
3636
br label %7
3737

3838
7: ; preds = %5, %1
3939
tail call void @llvm.nvvm.barrier0() #1
40-
%8 = load i32, i32 addrspace(3)* @foo.l.0, align 4
41-
%9 = getelementptr inbounds i32, i32 addrspace(1)* %0, i32 %2
42-
store i32 %8, i32 addrspace(1)* %9, align 4
40+
%8 = load i32, ptr addrspace(3) @foo.l.0, align 4
41+
%9 = getelementptr inbounds i32, ptr addrspace(1) %0, i32 %2
42+
store i32 %8, ptr addrspace(1) %9, align 4
4343
ret void
4444
}
4545

‎llvm/test/CodeGen/AMDGPU/global-offset-dbg.ll

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -7,14 +7,14 @@ target triple = "amdgcn-amd-amdhsa"
77

88
; This test checks that debug information on functions and callsites are preserved
99

10-
declare i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
10+
declare ptr addrspace(5) @llvm.amdgcn.implicit.offset()
1111
; CHECK-NOT: llvm.amdgcn.implicit.offset
1212

1313
define weak_odr dso_local i64 @_ZTS14other_function() !dbg !11 {
14-
; CHECK: define weak_odr dso_local i64 @_ZTS14other_function(i32 addrspace(5)* %0) !dbg !11 {
15-
%1 = tail call i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
16-
%2 = getelementptr inbounds i32, i32 addrspace(5)* %1, i64 2
17-
%3 = load i32, i32 addrspace(5)* %2, align 4
14+
; CHECK: define weak_odr dso_local i64 @_ZTS14other_function(ptr addrspace(5) %0) !dbg !11 {
15+
%1 = tail call ptr addrspace(5) @llvm.amdgcn.implicit.offset()
16+
%2 = getelementptr inbounds i32, ptr addrspace(5) %1, i64 2
17+
%3 = load i32, ptr addrspace(5) %2, align 4
1818
%4 = zext i32 %3 to i64
1919
ret i64 %4
2020
}
@@ -24,15 +24,15 @@ define weak_odr dso_local void @_ZTS14example_kernel() !dbg !14 {
2424
; CHECK: define weak_odr dso_local void @_ZTS14example_kernel() !dbg !14 {
2525
entry:
2626
%0 = call i64 @_ZTS14other_function(), !dbg !15
27-
; CHECK: %3 = call i64 @_ZTS14other_function(i32 addrspace(5)* %2), !dbg !15
27+
; CHECK: %2 = call i64 @_ZTS14other_function(ptr addrspace(5) %1), !dbg !15
2828
ret void
2929
}
3030

31-
; CHECK: define weak_odr dso_local void @_ZTS14example_kernel_with_offset([3 x i32]* byref([3 x i32]) %0) !dbg !16 {
31+
; CHECK: define weak_odr dso_local void @_ZTS14example_kernel_with_offset(ptr byref([3 x i32]) %0) !dbg !16 {
3232
; CHECK: %1 = alloca [3 x i32], align 4, addrspace(5), !dbg !17
33-
; CHECK: %2 = bitcast [3 x i32] addrspace(5)* %1 to i32 addrspace(5)*, !dbg !17
34-
; CHECK: call void @llvm.memcpy.p5i8.p4i8.i64(i8 addrspace(5)* align 4 %4, i8 addrspace(4)* align 1 %3, i64 12, i1 false), !dbg !17
35-
; CHECK: %5 = call i64 @_ZTS14other_function(i32 addrspace(5)* %2), !dbg !17
33+
; CHECK: %2 = addrspacecast ptr %0 to ptr addrspace(4), !dbg !17
34+
; CHECK: call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 4 %1, ptr addrspace(4) align 1 %2, i64 12, i1 false), !dbg !17
35+
; CHECK: %3 = call i64 @_ZTS14other_function(ptr addrspace(5) %1), !dbg !17
3636

3737
!llvm.dbg.cu = !{!0}
3838
!llvm.module.flags = !{!3, !4}
@@ -43,7 +43,7 @@ entry:
4343
!2 = !{}
4444
!3 = !{i32 2, !"Dwarf Version", i32 4}
4545
!4 = !{i32 2, !"Debug Info Version", i32 3}
46-
!5 = distinct !{void ()* @_ZTS14example_kernel, !"kernel", i32 1}
46+
!5 = distinct !{ptr @_ZTS14example_kernel, !"kernel", i32 1}
4747
!6 = !{i32 1, i32 4}
4848
!7 = !{null, !"align", i32 8, !"align", i32 65544, !"align", i32 131080}
4949
!8 = !{null, !"align", i32 16}

‎llvm/test/CodeGen/AMDGPU/global-offset-invalid-triple.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:3
77

88
; This test checks that the pass does not run on nvcl triples.
99

10-
declare i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
10+
declare ptr addrspace(5) @llvm.amdgcn.implicit.offset()
1111

1212
define weak_odr dso_local i64 @_ZTS14other_function() {
13-
%1 = tail call i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
14-
%2 = getelementptr inbounds i32, i32 addrspace(5)* %1, i64 2
15-
%3 = load i32, i32 addrspace(5)* %2, align 4
13+
%1 = tail call ptr addrspace(5) @llvm.amdgcn.implicit.offset()
14+
%2 = getelementptr inbounds i32, ptr addrspace(5) %1, i64 2
15+
%3 = load i32, ptr addrspace(5) %2, align 4
1616
%4 = zext i32 %3 to i64
1717
ret i64 %4
1818
}
@@ -26,7 +26,7 @@ entry:
2626

2727
!amdgcn.annotations = !{!0, !1, !2, !1, !3, !3, !3, !3, !4, !4, !3}
2828

29-
!0 = distinct !{void ()* @_ZTS14example_kernel, !"kernel", i32 1}
29+
!0 = distinct !{ptr @_ZTS14example_kernel, !"kernel", i32 1}
3030
!1 = !{null, !"align", i32 8}
3131
!2 = !{null, !"align", i32 8, !"align", i32 65544, !"align", i32 131080}
3232
!3 = !{null, !"align", i32 16}

‎llvm/test/CodeGen/AMDGPU/global-offset-multiple-calls-from-one-function.ll

Lines changed: 24 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -11,23 +11,23 @@ target triple = "amdgcn-amd-amdhsa"
1111
; to other functions that has a variant that takes an offset parameter will have
1212
; all calls redirected to the corresponding variants.
1313

14-
declare i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
15-
; CHECK-NOT: declare i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
14+
declare ptr addrspace(5) @llvm.amdgcn.implicit.offset()
15+
; CHECK-NOT: declare ptr addrspace(5) @llvm.amdgcn.implicit.offset()
1616

1717
define weak_odr dso_local i64 @_ZTS14other_function() {
18-
; CHECK: define weak_odr dso_local i64 @_ZTS14other_function(i32 addrspace(5)* %0) {
19-
%1 = tail call i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
20-
; CHECK-NOT: tail call i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
21-
%2 = getelementptr inbounds i32, i32 addrspace(5)* %1, i64 2
22-
; CHECK: %2 = getelementptr inbounds i32, i32 addrspace(5)* %0, i64 2
23-
%3 = load i32, i32 addrspace(5)* %2, align 4
18+
; CHECK: define weak_odr dso_local i64 @_ZTS14other_function(ptr addrspace(5) %0) {
19+
%1 = tail call ptr addrspace(5) @llvm.amdgcn.implicit.offset()
20+
; CHECK-NOT: tail call ptr addrspace(5)* @llvm.amdgcn.implicit.offset()
21+
%2 = getelementptr inbounds i32, ptr addrspace(5) %1, i64 2
22+
; CHECK: %2 = getelementptr inbounds i32, ptr addrspace(5) %0, i64 2
23+
%3 = load i32, ptr addrspace(5) %2, align 4
2424
%4 = zext i32 %3 to i64
2525

26-
%5 = tail call i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
27-
; CHECK-NOT: tail call i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
28-
%6 = getelementptr inbounds i32, i32 addrspace(5)* %5, i64 2
29-
; CHECK: %5 = getelementptr inbounds i32, i32 addrspace(5)* %0, i64 2
30-
%7 = load i32, i32 addrspace(5)* %6, align 4
26+
%5 = tail call ptr addrspace(5) @llvm.amdgcn.implicit.offset()
27+
; CHECK-NOT: tail call ptr addrspace(5)* @llvm.amdgcn.implicit.offset()
28+
%6 = getelementptr inbounds i32, ptr addrspace(5) %5, i64 2
29+
; CHECK: %5 = getelementptr inbounds i32, ptr addrspace(5) %0, i64 2
30+
%7 = load i32, ptr addrspace(5) %6, align 4
3131
%8 = zext i32 %7 to i64
3232

3333
ret i64 %4
@@ -37,32 +37,31 @@ define weak_odr dso_local i64 @_ZTS14other_function() {
3737
define weak_odr dso_local void @_ZTS14example_kernel() {
3838
entry:
3939
; CHECK: %0 = alloca [3 x i32], align 4, addrspace(5)
40-
; CHECK: %1 = bitcast [3 x i32] addrspace(5)* %0 to i8 addrspace(5)*
41-
; CHECK: call void @llvm.memset.p5i8.i64(i8 addrspace(5)* nonnull align 4 dereferenceable(12) %1, i8 0, i64 12, i1 false)
42-
; CHECK: %2 = getelementptr inbounds [3 x i32], [3 x i32] addrspace(5)* %0, i32 0, i32 0
40+
; CHECK: call void @llvm.memset.p5.i64(ptr addrspace(5) nonnull align 4 dereferenceable(12) %0, i8 0, i64 12, i1 false)
41+
; CHECK: %1 = getelementptr inbounds [3 x i32], ptr addrspace(5) %0, i32 0, i32 0
4342
%0 = call i64 @_ZTS14other_function()
44-
; CHECK: %3 = call i64 @_ZTS14other_function(i32 addrspace(5)* %2)
43+
; CHECK: %2 = call i64 @_ZTS14other_function(ptr addrspace(5) %1)
4544
%1 = call i64 @_ZTS14other_function()
46-
; CHECK: %4 = call i64 @_ZTS14other_function(i32 addrspace(5)* %2)
45+
; CHECK: %3 = call i64 @_ZTS14other_function(ptr addrspace(5) %1)
4746
ret void
4847
}
4948

50-
; CHECK: define weak_odr dso_local void @_ZTS14example_kernel_with_offset([3 x i32]* byref([3 x i32]) %0) {
49+
; CHECK: define weak_odr dso_local void @_ZTS14example_kernel_with_offset(ptr byref([3 x i32]) %0) {
5150
; CHECK: entry:
5251
; CHECK: %1 = alloca [3 x i32], align 4, addrspace(5)
53-
; CHECK: %2 = bitcast [3 x i32] addrspace(5)* %1 to i32 addrspace(5)*
54-
; CHECK: call void @llvm.memcpy.p5i8.p4i8.i64(i8 addrspace(5)* align 4 %4, i8 addrspace(4)* align 1 %3, i64 12, i1 false)
55-
; CHECK: %5 = call i64 @_ZTS14other_function(i32 addrspace(5)* %2)
56-
; CHECK: %6 = call i64 @_ZTS14other_function(i32 addrspace(5)* %2)
52+
; CHECK: %2 = addrspacecast ptr %0 to ptr addrspace(4)
53+
; CHECK: call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 4 %1, ptr addrspace(4) align 1 %2, i64 12, i1 false)
54+
; CHECK: %3 = call i64 @_ZTS14other_function(ptr addrspace(5) %1)
55+
; CHECK: %4 = call i64 @_ZTS14other_function(ptr addrspace(5) %1)
5756
; CHECK: ret void
5857
; CHECK: }
5958

6059
!amdgcn.annotations = !{!0, !1, !2, !1, !3, !3, !3, !3, !4, !4, !3}
6160
; CHECK: !amdgcn.annotations = !{!0, !1, !2, !1, !3, !3, !3, !3, !4, !4, !3, !5}
6261

63-
!0 = distinct !{void ()* @_ZTS14example_kernel, !"kernel", i32 1}
62+
!0 = distinct !{ptr @_ZTS14example_kernel, !"kernel", i32 1}
6463
!1 = !{null, !"align", i32 8}
6564
!2 = !{null, !"align", i32 8, !"align", i32 65544, !"align", i32 131080}
6665
!3 = !{null, !"align", i32 16}
6766
!4 = !{null, !"align", i32 16, !"align", i32 65552, !"align", i32 131088}
68-
; CHECK: !5 = !{void ([3 x i32]*)* @_ZTS14example_kernel_with_offset, !"kernel", i32 1}
67+
; CHECK: !5 = !{ptr @_ZTS14example_kernel_with_offset, !"kernel", i32 1}

‎llvm/test/CodeGen/AMDGPU/global-offset-multiple-entry-points.ll

Lines changed: 37 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@ target triple = "amdgcn-amd-amdhsa"
77

88
; This test checks that the pass works with multiple entry points.
99

10-
declare i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
11-
; CHECK-NOT: declare i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
10+
declare ptr addrspace(5) @llvm.amdgcn.implicit.offset()
11+
; CHECK-NOT: declare ptr addrspace(5) @llvm.amdgcn.implicit.offset()
1212

1313
; This function is a kernel entry point that does not use global offset. It will
1414
; not get a clone with a global offset parameter.
@@ -19,93 +19,91 @@ entry:
1919
}
2020

2121
define weak_odr dso_local i64 @_ZTS15common_function() {
22-
; CHECK: define weak_odr dso_local i64 @_ZTS15common_function(i32 addrspace(5)* %0) {
23-
%1 = tail call i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
24-
; CHECK-NOT: tail call i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
25-
; CHECK: %2 = getelementptr inbounds i32, i32 addrspace(5)* %0, i64 2
26-
%2 = getelementptr inbounds i32, i32 addrspace(5)* %1, i64 2
27-
%3 = load i32, i32 addrspace(5)* %2, align 4
22+
; CHECK: define weak_odr dso_local i64 @_ZTS15common_function(ptr addrspace(5) %0) {
23+
%1 = tail call ptr addrspace(5) @llvm.amdgcn.implicit.offset()
24+
; CHECK-NOT: tail call ptr addrspace(5) @llvm.amdgcn.implicit.offset()
25+
; CHECK: %2 = getelementptr inbounds i32, ptr addrspace(5) %0, i64 2
26+
%2 = getelementptr inbounds i32, ptr addrspace(5) %1, i64 2
27+
%3 = load i32, ptr addrspace(5) %2, align 4
2828
%4 = zext i32 %3 to i64
2929
ret i64 %4
3030
}
3131

3232
define weak_odr dso_local i64 @_ZTS14first_function() {
33-
; CHECK: define weak_odr dso_local i64 @_ZTS14first_function(i32 addrspace(5)* %0) {
33+
; CHECK: define weak_odr dso_local i64 @_ZTS14first_function(ptr addrspace(5) %0) {
3434
%1 = call i64 @_ZTS15common_function()
35-
; CHECK: %2 = call i64 @_ZTS15common_function(i32 addrspace(5)* %0)
35+
; CHECK: %2 = call i64 @_ZTS15common_function(ptr addrspace(5) %0)
3636
ret i64 %1
3737
}
3838

3939
; Function Attrs: noinline
4040
define weak_odr dso_local void @_ZTS12first_kernel() {
4141
entry:
4242
; CHECK: %0 = alloca [3 x i32], align 4
43-
; CHECK: %1 = bitcast [3 x i32] addrspace(5)* %0 to i8 addrspace(5)*
44-
; CHECK: call void @llvm.memset.p5i8.i64(i8 addrspace(5)* nonnull align 4 dereferenceable(12) %1, i8 0, i64 12, i1 false)
45-
; CHECK: %2 = getelementptr inbounds [3 x i32], [3 x i32] addrspace(5)* %0, i32 0, i32 0
43+
; CHECK: call void @llvm.memset.p5.i64(ptr addrspace(5) nonnull align 4 dereferenceable(12) %0, i8 0, i64 12, i1 false)
44+
; CHECK: %1 = getelementptr inbounds [3 x i32], ptr addrspace(5) %0, i32 0, i32 0
4645
%0 = call i64 @_ZTS14first_function()
47-
; CHECK: %3 = call i64 @_ZTS14first_function(i32 addrspace(5)* %2)
46+
; CHECK: %2 = call i64 @_ZTS14first_function(ptr addrspace(5) %1)
4847
ret void
4948
}
5049

51-
; CHECK: define weak_odr dso_local void @_ZTS12first_kernel_with_offset([3 x i32]* byref([3 x i32]) %0) {
50+
; CHECK: define weak_odr dso_local void @_ZTS12first_kernel_with_offset(ptr byref([3 x i32]) %0) {
5251
; CHECK: entry:
5352
; CHECK: %1 = alloca [3 x i32], align 4, addrspace(5)
54-
; CHECK: %2 = bitcast [3 x i32] addrspace(5)* %1 to i32 addrspace(5)*
55-
; CHECK: call void @llvm.memcpy.p5i8.p4i8.i64(i8 addrspace(5)* align 4 %4, i8 addrspace(4)* align 1 %3, i64 12, i1 false)
56-
; CHECK: %5 = call i64 @_ZTS14first_function(i32 addrspace(5)* %2)
53+
; CHECK: %2 = addrspacecast ptr %0 to ptr addrspace(4)
54+
; CHECK: call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 4 %1, ptr addrspace(4) align 1 %2, i64 12, i1 false)
55+
; CHECK: %3 = call i64 @_ZTS14first_function(ptr addrspace(5) %1)
5756
; CHECK: ret void
5857
; CHECK: }
5958

6059
define weak_odr dso_local i64 @_ZTS15second_function() {
61-
; CHECK: define weak_odr dso_local i64 @_ZTS15second_function(i32 addrspace(5)* %0) {
60+
; CHECK: define weak_odr dso_local i64 @_ZTS15second_function(ptr addrspace(5) %0) {
6261
%1 = call i64 @_ZTS15common_function()
63-
; CHECK: %2 = call i64 @_ZTS15common_function(i32 addrspace(5)* %0)
62+
; CHECK: %2 = call i64 @_ZTS15common_function(ptr addrspace(5) %0)
6463
ret i64 %1
6564
}
6665

6766
; Function Attrs: noinline
6867
define weak_odr dso_local void @_ZTS13second_kernel() {
6968
entry:
7069
; CHECK: %0 = alloca [3 x i32], align 4
71-
; CHECK: %1 = bitcast [3 x i32] addrspace(5)* %0 to i8 addrspace(5)*
72-
; CHECK: call void @llvm.memset.p5i8.i64(i8 addrspace(5)* nonnull align 4 dereferenceable(12) %1, i8 0, i64 12, i1 false)
73-
; CHECK: %2 = getelementptr inbounds [3 x i32], [3 x i32] addrspace(5)* %0, i32 0, i32 0
70+
; CHECK: call void @llvm.memset.p5.i64(ptr addrspace(5) nonnull align 4 dereferenceable(12) %0, i8 0, i64 12, i1 false)
71+
; CHECK: %1 = getelementptr inbounds [3 x i32], ptr addrspace(5) %0, i32 0, i32 0
7472
%0 = call i64 @_ZTS15second_function()
75-
; CHECK: %3 = call i64 @_ZTS15second_function(i32 addrspace(5)* %2)
73+
; CHECK: %2 = call i64 @_ZTS15second_function(ptr addrspace(5) %1)
7674
ret void
7775
}
7876

79-
; CHECK: define weak_odr dso_local void @_ZTS13second_kernel_with_offset([3 x i32]* byref([3 x i32]) %0) {
77+
; CHECK: define weak_odr dso_local void @_ZTS13second_kernel_with_offset(ptr byref([3 x i32]) %0) {
8078
; CHECK: entry:
8179
; CHECK: %1 = alloca [3 x i32], align 4, addrspace(5)
82-
; CHECK: %2 = bitcast [3 x i32] addrspace(5)* %1 to i32 addrspace(5)*
83-
; CHEKC: call void @llvm.memcpy.p5i8.p4i8.i64(i8 addrspace(5)* align 4 %4, i8 addrspace(4)* align 1 %3, i64 12, i1 false)
84-
; CHECK: %5 = call i64 @_ZTS15second_function(i32 addrspace(5)* %2)
80+
; CHECK: %2 = addrspacecast ptr %0 to ptr addrspace(4)
81+
; CHECK: call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 4 %1, ptr addrspace(4) align 1 %2, i64 12, i1 false)
82+
; CHECK: %3 = call i64 @_ZTS15second_function(ptr addrspace(5) %1)
8583
; CHECK: ret void
8684
; CHECK: }
8785

8886
; This function doesn't get called by a kernel entry point.
8987
define weak_odr dso_local i64 @_ZTS15no_entry_point() {
90-
; CHECK: define weak_odr dso_local i64 @_ZTS15no_entry_point(i32 addrspace(5)* %0) {
91-
%1 = tail call i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
92-
; CHECK-NOT: tail call i32 addrspace(5)* @llvm.amdgcn.implicit.offset()
93-
%2 = getelementptr inbounds i32, i32 addrspace(5)* %1, i64 2
94-
; CHECK: %2 = getelementptr inbounds i32, i32 addrspace(5)* %0, i64 2
95-
%3 = load i32, i32 addrspace(5)* %2, align 4
88+
; CHECK: define weak_odr dso_local i64 @_ZTS15no_entry_point(ptr addrspace(5) %0) {
89+
%1 = tail call ptr addrspace(5) @llvm.amdgcn.implicit.offset()
90+
; CHECK-NOT: tail call ptr addrspace(5) @llvm.amdgcn.implicit.offset()
91+
%2 = getelementptr inbounds i32, ptr addrspace(5) %1, i64 2
92+
; CHECK: %2 = getelementptr inbounds i32, ptr addrspace(5) %0, i64 2
93+
%3 = load i32, ptr addrspace(5) %2, align 4
9694
%4 = zext i32 %3 to i64
9795
ret i64 %4
9896
}
9997

10098
!amdgcn.annotations = !{!0, !1, !2, !1, !3, !3, !3, !3, !4, !4, !3, !5, !6}
10199
; CHECK: !amdgcn.annotations = !{!0, !1, !2, !1, !3, !3, !3, !3, !4, !4, !3, !5, !6, !7, !8}
102100

103-
!0 = distinct !{void ()* @_ZTS12first_kernel, !"kernel", i32 1}
101+
!0 = distinct !{ptr @_ZTS12first_kernel, !"kernel", i32 1}
104102
!1 = !{null, !"align", i32 8}
105103
!2 = !{null, !"align", i32 8, !"align", i32 65544, !"align", i32 131080}
106104
!3 = !{null, !"align", i32 16}
107105
!4 = !{null, !"align", i32 16, !"align", i32 65552, !"align", i32 131088}
108-
!5 = distinct !{void ()* @_ZTS13second_kernel, !"kernel", i32 1}
109-
!6 = distinct !{void ()* @_ZTS12third_kernel, !"kernel", i32 1}
110-
; CHECK: !7 = !{void ([3 x i32]*)* @_ZTS13second_kernel_with_offset, !"kernel", i32 1}
111-
; CHECK: !8 = !{void ([3 x i32]*)* @_ZTS12first_kernel_with_offset, !"kernel", i32 1}
106+
!5 = distinct !{ptr @_ZTS13second_kernel, !"kernel", i32 1}
107+
!6 = distinct !{ptr @_ZTS12third_kernel, !"kernel", i32 1}
108+
; CHECK: !7 = !{ptr @_ZTS13second_kernel_with_offset, !"kernel", i32 1}
109+
; CHECK: !8 = !{ptr @_ZTS12first_kernel_with_offset, !"kernel", i32 1}

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