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Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"
This reverts commit 31009f0. It seems to be causing SVE VLA buildbot failures and has introduced a genuine regression. Reverting for now.
1 parent fe17ce0 commit ba471ba

21 files changed

+80
-60
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2647,9 +2647,9 @@ class TargetLoweringBase {
26472647
getApproximateEVTForLLT(ToTy, DL, Ctx));
26482648
}
26492649

2650-
/// Return true if sign-extension of value \p V from FromTy to ToTy is
2651-
/// cheaper than zero-extension, where \p V can be SDValue() if unknown.
2652-
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy, SDValue V) const {
2650+
/// Return true if sign-extension from FromTy to ToTy is cheaper than
2651+
/// zero-extension.
2652+
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
26532653
return false;
26542654
}
26552655

‎llvm/lib/CodeGen/CodeGenPrepare.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7004,7 +7004,7 @@ bool CodeGenPrepare::optimizeSwitchInst(SwitchInst *SI) {
70047004
// matching the argument extension instead.
70057005
Instruction::CastOps ExtType = Instruction::ZExt;
70067006
// Some targets prefer SExt over ZExt.
7007-
if (TLI->isSExtCheaperThanZExt(OldVT, RegType, SDValue()))
7007+
if (TLI->isSExtCheaperThanZExt(OldVT, RegType))
70087008
ExtType = Instruction::SExt;
70097009

70107010
if (auto *Arg = dyn_cast<Argument>(Cond)) {

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1704,7 +1704,7 @@ void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
17041704
SDValue OpL = GetPromotedInteger(LHS);
17051705
SDValue OpR = GetPromotedInteger(RHS);
17061706

1707-
if (TLI.isSExtCheaperThanZExt(LHS.getValueType(), OpL.getValueType(), LHS)) {
1707+
if (TLI.isSExtCheaperThanZExt(LHS.getValueType(), OpL.getValueType())) {
17081708
// The target would prefer to promote the comparison operand with sign
17091709
// extension. Honor that unless the promoted values are already zero
17101710
// extended.

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -283,7 +283,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
283283
EVT OldVT = Op.getValueType();
284284
SDLoc DL(Op);
285285
Op = GetPromotedInteger(Op);
286-
if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType(), Op))
286+
if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType()))
287287
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op,
288288
DAG.getValueType(OldVT));
289289
return DAG.getZeroExtendInReg(Op, DL, OldVT);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4767,7 +4767,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
47674767
C->isTargetOpcode(), C->isOpaque());
47684768
case ISD::ANY_EXTEND:
47694769
// Some targets like RISCV prefer to sign extend some types.
4770-
if (TLI->isSExtCheaperThanZExt(Operand.getValueType(), VT, Operand))
4770+
if (TLI->isSExtCheaperThanZExt(Operand.getValueType(), VT))
47714771
return getConstant(Val.sextOrTrunc(VT.getSizeInBits()), DL, VT,
47724772
C->isTargetOpcode(), C->isOpaque());
47734773
return getConstant(Val.zextOrTrunc(VT.getSizeInBits()), DL, VT,

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3844,7 +3844,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
38443844
} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
38453845
(Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
38463846
!isSExtCheaperThanZExt(cast<VTSDNode>(N0.getOperand(1))->getVT(),
3847-
OpVT, N0.getOperand(1))) {
3847+
OpVT)) {
38483848
EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
38493849
unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
38503850
EVT ExtDstTy = N0.getValueType();

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1138,14 +1138,6 @@ class AArch64TargetLowering : public TargetLowering {
11381138

11391139
bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1,
11401140
LLT Ty2) const override;
1141-
1142-
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT, SDValue V) const override {
1143-
if (!V)
1144-
return false;
1145-
if (ConstantSDNode *C = isConstOrConstSplat(V))
1146-
return C->getAPIntValue().isNegative();
1147-
return false;
1148-
}
11491141
};
11501142

11511143
namespace AArch64 {

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1198,8 +1198,7 @@ bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11981198
return TargetLowering::isZExtFree(Val, VT2);
11991199
}
12001200

1201-
bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT,
1202-
SDValue V) const {
1201+
bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
12031202
return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
12041203
}
12051204

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -326,7 +326,7 @@ class RISCVTargetLowering : public TargetLowering {
326326
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
327327
bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
328328
bool isZExtFree(SDValue Val, EVT VT2) const override;
329-
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT, SDValue V) const override;
329+
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
330330
bool isCheapToSpeculateCttz() const override;
331331
bool isCheapToSpeculateCtlz() const override;
332332
bool hasAndNotCompare(SDValue Y) const override;

‎llvm/test/CodeGen/AArch64/arm64-vshuffle.ll

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,18 @@ entry:
1414
ret <8 x i1> %Shuff
1515
}
1616

17+
; CHECK: lCPI1_0:
18+
; CHECK: .byte 0 ; 0x0
19+
; CHECK: .byte 0 ; 0x0
20+
; CHECK: .byte 0 ; 0x0
21+
; CHECK: .byte 0 ; 0x0
22+
; CHECK: .byte 1 ; 0x1
23+
; CHECK: .byte 0 ; 0x0
24+
; CHECK: .byte 0 ; 0x0
25+
; CHECK: .byte 0 ; 0x0
1726
; CHECK: test2
18-
; CHECK: movi d{{[0-9]+}}, #0x0000ff00000000
27+
; CHECK: adrp x[[REG2:[0-9]+]], lCPI1_0@PAGE
28+
; CHECK: ldr d[[REG1:[0-9]+]], [x[[REG2]], lCPI1_0@PAGEOFF]
1929
define <8 x i1>@test2() {
2030
bb:
2131
%Shuff = shufflevector <8 x i1> zeroinitializer,
@@ -26,7 +36,7 @@ bb:
2636
}
2737

2838
; CHECK: test3
29-
; CHECK: movi.2d v{{[0-9]+}}, #0x0000ff000000ff
39+
; CHECK: movi.4s v{{[0-9]+}}, #1
3040
define <16 x i1> @test3(i1* %ptr, i32 %v) {
3141
bb:
3242
%Shuff = shufflevector <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, <16 x i1> undef,
@@ -35,13 +45,11 @@ bb:
3545
i32 14, i32 0>
3646
ret <16 x i1> %Shuff
3747
}
38-
39-
4048
; CHECK: lCPI3_0:
4149
; CHECK: .byte 0 ; 0x0
4250
; CHECK: .byte 0 ; 0x0
4351
; CHECK: .byte 0 ; 0x0
44-
; CHECK: .byte 255 ; 0xff
52+
; CHECK: .byte 1 ; 0x1
4553
; CHECK: .byte 0 ; 0x0
4654
; CHECK: .byte 0 ; 0x0
4755
; CHECK: .byte 0 ; 0x0

‎llvm/test/CodeGen/AArch64/arm64_32-atomics.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -249,7 +249,7 @@ define {i8*, i1} @test_cmpxchg_ptr(i8** %addr, i8* %cmp, i8* %new) {
249249
; CHECK: stlxr [[SUCCESS:w[0-9]+]], w2, [x0]
250250
; CHECK: cbnz [[SUCCESS]], [[LOOP]]
251251

252-
; CHECK: mov w1, #-1
252+
; CHECK: mov w1, #1
253253
; CHECK: mov w0, [[OLD]]
254254
; CHECK: ret
255255

‎llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) {
1515
; CHECK-NEXT: stlxr w8, w2, [x0]
1616
; CHECK-NEXT: cbnz w8, LBB0_1
1717
; CHECK-NEXT: ; %bb.3:
18-
; CHECK-NEXT: mov w0, #-1
18+
; CHECK-NEXT: mov w0, #1
1919
; CHECK-NEXT: ret
2020
; CHECK-NEXT: LBB0_4: ; %cmpxchg.nostore
2121
; CHECK-NEXT: mov w0, wzr
@@ -64,7 +64,7 @@ define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) {
6464
; CHECK-NEXT: stlxrb w9, w2, [x0]
6565
; CHECK-NEXT: cbnz w9, LBB1_1
6666
; CHECK-NEXT: ; %bb.3:
67-
; CHECK-NEXT: mov w8, #-1
67+
; CHECK-NEXT: mov w8, #1
6868
; CHECK-NEXT: eor w0, w8, #0x1
6969
; CHECK-NEXT: ret
7070
; CHECK-NEXT: LBB1_4: ; %cmpxchg.nostore
@@ -188,7 +188,7 @@ define i1 @test_conditional2(i32 %a, i32 %b, i32* %c) {
188188
; CHECK-NEXT: stlxr w8, w20, [x19]
189189
; CHECK-NEXT: cbnz w8, LBB3_1
190190
; CHECK-NEXT: ; %bb.3:
191-
; CHECK-NEXT: mov w8, #-1
191+
; CHECK-NEXT: mov w8, #1
192192
; CHECK-NEXT: b LBB3_5
193193
; CHECK-NEXT: LBB3_4: ; %cmpxchg.nostore
194194
; CHECK-NEXT: mov w8, wzr

‎llvm/test/CodeGen/AArch64/dag-numsignbits.ll

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,18 @@ define void @signbits_vXi1(<4 x i16> %a1) {
88
; CHECK: // %bb.0:
99
; CHECK-NEXT: adrp x8, .LCPI0_0
1010
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
11-
; CHECK-NEXT: movi v2.4h, #1
12-
; CHECK-NEXT: dup v0.4h, v0.h[0]
1311
; CHECK-NEXT: mov w1, wzr
12+
; CHECK-NEXT: dup v0.4h, v0.h[0]
1413
; CHECK-NEXT: mov w2, wzr
1514
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0]
15+
; CHECK-NEXT: adrp x8, .LCPI0_1
1616
; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
17-
; CHECK-NEXT: cmgt v0.4h, v2.4h, v0.4h
17+
; CHECK-NEXT: movi v1.4h, #1
18+
; CHECK-NEXT: cmgt v0.4h, v1.4h, v0.4h
19+
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_1]
20+
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
21+
; CHECK-NEXT: shl v0.4h, v0.4h, #15
22+
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
1823
; CHECK-NEXT: umov w0, v0.h[0]
1924
; CHECK-NEXT: umov w3, v0.h[3]
2025
; CHECK-NEXT: b foo

‎llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll

Lines changed: 6 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -25,10 +25,8 @@ bb2:
2525
define <2 x i32> @icmp_constfold_v2i32(<2 x i32> %a) {
2626
; CHECK-LABEL: icmp_constfold_v2i32:
2727
; CHECK: ; %bb.0:
28-
; CHECK-NEXT: movi.2d v0, #0xffffffffffffffff
29-
; CHECK-NEXT: ; %bb.1: ; %bb2
30-
; CHECK-NEXT: movi.2s v1, #1
31-
; CHECK-NEXT: and.8b v0, v0, v1
28+
; CHECK-NEXT: movi.2s v0, #1
29+
; CHECK-NEXT: and.8b v0, v0, v0
3230
; CHECK-NEXT: ret
3331
%1 = icmp eq <2 x i32> %a, %a
3432
br label %bb2
@@ -57,10 +55,9 @@ bb2:
5755
define <4 x i32> @icmp_constfold_v4i32(<4 x i32> %a) {
5856
; CHECK-LABEL: icmp_constfold_v4i32:
5957
; CHECK: ; %bb.0:
60-
; CHECK-NEXT: movi.2d v0, #0xffffffffffffffff
58+
; CHECK-NEXT: movi.4h v0, #1
6159
; CHECK-NEXT: ; %bb.1: ; %bb2
62-
; CHECK-NEXT: movi.4h v1, #1
63-
; CHECK-NEXT: and.8b v0, v0, v1
60+
; CHECK-NEXT: and.8b v0, v0, v0
6461
; CHECK-NEXT: ushll.4s v0, v0, #0
6562
; CHECK-NEXT: ret
6663
%1 = icmp eq <4 x i32> %a, %a
@@ -88,10 +85,8 @@ bb2:
8885
define <16 x i8> @icmp_constfold_v16i8(<16 x i8> %a) {
8986
; CHECK-LABEL: icmp_constfold_v16i8:
9087
; CHECK: ; %bb.0:
91-
; CHECK-NEXT: movi.2d v0, #0xffffffffffffffff
92-
; CHECK-NEXT: ; %bb.1: ; %bb2
93-
; CHECK-NEXT: movi.16b v1, #1
94-
; CHECK-NEXT: and.16b v0, v0, v1
88+
; CHECK-NEXT: movi.16b v0, #1
89+
; CHECK-NEXT: and.16b v0, v0, v0
9590
; CHECK-NEXT: ret
9691
%1 = icmp eq <16 x i8> %a, %a
9792
br label %bb2

‎llvm/test/CodeGen/AArch64/funnel-shift.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ declare i7 @llvm.fshl.i7(i7, i7, i7)
9393
define i7 @fshl_i7_const_fold() {
9494
; CHECK-LABEL: fshl_i7_const_fold:
9595
; CHECK: // %bb.0:
96-
; CHECK-NEXT: mov w0, #-61
96+
; CHECK-NEXT: mov w0, #67
9797
; CHECK-NEXT: ret
9898
%f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
9999
ret i7 %f
@@ -102,7 +102,7 @@ define i7 @fshl_i7_const_fold() {
102102
define i8 @fshl_i8_const_fold_overshift_1() {
103103
; CHECK-LABEL: fshl_i8_const_fold_overshift_1:
104104
; CHECK: // %bb.0:
105-
; CHECK-NEXT: mov w0, #-128
105+
; CHECK-NEXT: mov w0, #128
106106
; CHECK-NEXT: ret
107107
%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 15)
108108
ret i8 %f
@@ -164,7 +164,7 @@ define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) {
164164
define i8 @fshl_i8_const_fold() {
165165
; CHECK-LABEL: fshl_i8_const_fold:
166166
; CHECK: // %bb.0:
167-
; CHECK-NEXT: mov w0, #-128
167+
; CHECK-NEXT: mov w0, #128
168168
; CHECK-NEXT: ret
169169
%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)
170170
ret i8 %f
@@ -241,7 +241,7 @@ define i7 @fshr_i7_const_fold() {
241241
define i8 @fshr_i8_const_fold_overshift_1() {
242242
; CHECK-LABEL: fshr_i8_const_fold_overshift_1:
243243
; CHECK: // %bb.0:
244-
; CHECK-NEXT: mov w0, #-2
244+
; CHECK-NEXT: mov w0, #254
245245
; CHECK-NEXT: ret
246246
%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 15)
247247
ret i8 %f
@@ -250,7 +250,7 @@ define i8 @fshr_i8_const_fold_overshift_1() {
250250
define i8 @fshr_i8_const_fold_overshift_2() {
251251
; CHECK-LABEL: fshr_i8_const_fold_overshift_2:
252252
; CHECK: // %bb.0:
253-
; CHECK-NEXT: mov w0, #-31
253+
; CHECK-NEXT: mov w0, #225
254254
; CHECK-NEXT: ret
255255
%f = call i8 @llvm.fshr.i8(i8 15, i8 15, i8 11)
256256
ret i8 %f
@@ -259,7 +259,7 @@ define i8 @fshr_i8_const_fold_overshift_2() {
259259
define i8 @fshr_i8_const_fold_overshift_3() {
260260
; CHECK-LABEL: fshr_i8_const_fold_overshift_3:
261261
; CHECK: // %bb.0:
262-
; CHECK-NEXT: mov w0, #-1
262+
; CHECK-NEXT: mov w0, #255
263263
; CHECK-NEXT: ret
264264
%f = call i8 @llvm.fshr.i8(i8 0, i8 255, i8 8)
265265
ret i8 %f
@@ -303,7 +303,7 @@ define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) {
303303
define i8 @fshr_i8_const_fold() {
304304
; CHECK-LABEL: fshr_i8_const_fold:
305305
; CHECK: // %bb.0:
306-
; CHECK-NEXT: mov w0, #-2
306+
; CHECK-NEXT: mov w0, #254
307307
; CHECK-NEXT: ret
308308
%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)
309309
ret i8 %f

‎llvm/test/CodeGen/AArch64/reduce-and.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -223,7 +223,8 @@ define i8 @test_redand_v3i8(<3 x i8> %a) {
223223
; CHECK-LABEL: test_redand_v3i8:
224224
; CHECK: // %bb.0:
225225
; CHECK-NEXT: and w8, w0, w1
226-
; CHECK-NEXT: and w0, w8, w2
226+
; CHECK-NEXT: and w8, w8, w2
227+
; CHECK-NEXT: and w0, w8, #0xff
227228
; CHECK-NEXT: ret
228229
;
229230
; GISEL-LABEL: test_redand_v3i8:

‎llvm/test/CodeGen/AArch64/redundant-copy-elim-empty-mbb.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ declare i8* @bar()
99

1010
; CHECK-LABEL: foo:
1111
; CHECK: tbz
12-
; CHECK: mov{{.*}}, #-1
12+
; CHECK: mov{{.*}}, #1
1313
; CHECK: ret
1414
; CHECK: bl bar
1515
; CHECK: cbnz

‎llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -177,7 +177,7 @@ define i1 @test_cross_bb(i32 addrspace(1)* %a, i1 %external_cond) gc "statepoint
177177
; CHECK-NEXT: bl consume
178178
; CHECK-NEXT: b .LBB8_3
179179
; CHECK-NEXT: .LBB8_2:
180-
; CHECK-NEXT: mov w19, #-1
180+
; CHECK-NEXT: mov w19, #1
181181
; CHECK-NEXT: .LBB8_3: // %common.ret
182182
; CHECK-NEXT: and w0, w19, #0x1
183183
; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload

‎llvm/test/CodeGen/AArch64/sve-vector-splat.ll

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,8 @@ define <vscale x 8 x i8> @sve_splat_8xi8(i8 %val) {
119119
define <vscale x 8 x i8> @sve_splat_8xi8_imm() {
120120
; CHECK-LABEL: sve_splat_8xi8_imm:
121121
; CHECK: // %bb.0:
122-
; CHECK-NEXT: mov z0.h, #-1 // =0xffffffffffffffff
122+
; CHECK-NEXT: mov w8, #255
123+
; CHECK-NEXT: mov z0.h, w8
123124
; CHECK-NEXT: ret
124125
%ins = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
125126
%splat = shufflevector <vscale x 8 x i8> %ins, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -150,7 +151,8 @@ define <vscale x 4 x i16> @sve_splat_4xi16(i16 %val) {
150151
define <vscale x 4 x i16> @sve_splat_4xi16_imm() {
151152
; CHECK-LABEL: sve_splat_4xi16_imm:
152153
; CHECK: // %bb.0:
153-
; CHECK-NEXT: mov z0.s, #-1 // =0xffffffffffffffff
154+
; CHECK-NEXT: mov w8, #65535
155+
; CHECK-NEXT: mov z0.s, w8
154156
; CHECK-NEXT: ret
155157
%ins = insertelement <vscale x 4 x i16> undef, i16 -1, i32 0
156158
%splat = shufflevector <vscale x 4 x i16> %ins, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -171,7 +173,8 @@ define <vscale x 2 x i32> @sve_splat_2xi32(i32 %val) {
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define <vscale x 2 x i32> @sve_splat_2xi32_imm() {
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; CHECK-LABEL: sve_splat_2xi32_imm:
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; CHECK: // %bb.0:
174-
; CHECK-NEXT: mov z0.d, #-1 // =0xffffffffffffffff
176+
; CHECK-NEXT: mov w8, #-1
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; CHECK-NEXT: mov z0.d, x8
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; CHECK-NEXT: ret
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%ins = insertelement <vscale x 2 x i32> undef, i32 -1, i32 0
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%splat = shufflevector <vscale x 2 x i32> %ins, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer

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