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Gang Chen
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[SYCL][ESIMD] - unary and shift operators (#3014)
Signed-off-by: Gang Y Chen <[email protected]>
1 parent 0b4a56d commit e7bcb57

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4 files changed

+73
-23
lines changed

4 files changed

+73
-23
lines changed

‎sycl/include/CL/sycl/INTEL/esimd/esimd.hpp

Lines changed: 22 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -234,15 +234,15 @@ template <typename Ty, int N> class simd {
234234

235235
#undef DEF_RELOP
236236

237-
#define DEF_LOGIC_OP(LOGIC_OP, OPASSIGN) \
238-
ESIMD_INLINE friend simd operator LOGIC_OP(const simd &X, const simd &Y) { \
237+
#define DEF_BITWISE_OP(BITWISE_OP, OPASSIGN) \
238+
ESIMD_INLINE friend simd operator BITWISE_OP(const simd &X, const simd &Y) { \
239239
static_assert(std::is_integral<Ty>(), "not integeral type"); \
240-
auto V2 = X.data() LOGIC_OP Y.data(); \
240+
auto V2 = X.data() BITWISE_OP Y.data(); \
241241
return simd(V2); \
242242
} \
243243
ESIMD_INLINE friend simd &operator OPASSIGN(simd &LHS, const simd &RHS) { \
244244
static_assert(std::is_integral<Ty>(), "not integeral type"); \
245-
auto V2 = LHS.data() LOGIC_OP RHS.data(); \
245+
auto V2 = LHS.data() BITWISE_OP RHS.data(); \
246246
LHS.write(convert<vector_type>(V2)); \
247247
return LHS; \
248248
} \
@@ -251,11 +251,13 @@ template <typename Ty, int N> class simd {
251251
return LHS; \
252252
}
253253

254-
DEF_LOGIC_OP(&, &=)
255-
DEF_LOGIC_OP(|, |=)
256-
DEF_LOGIC_OP(^, ^=)
254+
DEF_BITWISE_OP(&, &=)
255+
DEF_BITWISE_OP(|, |=)
256+
DEF_BITWISE_OP(^, ^=)
257+
DEF_BITWISE_OP(<<, <<=)
258+
DEF_BITWISE_OP(>>, >>=)
257259

258-
#undef DEF_LOGIC_OP
260+
#undef DEF_BITWISE_OP
259261

260262
// Operator ++, --
261263
simd &operator++() {
@@ -277,6 +279,18 @@ template <typename Ty, int N> class simd {
277279
return Ret;
278280
}
279281

282+
#define DEF_UNARY_OP(UNARY_OP) \
283+
simd operator UNARY_OP() { \
284+
auto V = UNARY_OP(data()); \
285+
return simd(V); \
286+
}
287+
DEF_UNARY_OP(!)
288+
DEF_UNARY_OP(~)
289+
DEF_UNARY_OP(+)
290+
DEF_UNARY_OP(-)
291+
292+
#undef DEF_UNARY_OP
293+
280294
/// \name Replicate
281295
/// Replicate simd instance given a region.
282296
/// @{

‎sycl/include/CL/sycl/INTEL/esimd/esimd_view.hpp

Lines changed: 29 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -247,38 +247,52 @@ template <typename BaseTy, typename RegionTy> class simd_view {
247247

248248
#undef DEF_RELOP
249249

250-
#define DEF_LOGIC_OP(LOGIC_OP, OPASSIGN) \
251-
ESIMD_INLINE friend auto operator LOGIC_OP(const simd_view &X, \
252-
const value_type &Y) { \
250+
#define DEF_BITWISE_OP(BITWISE_OP, OPASSIGN) \
251+
ESIMD_INLINE friend auto operator BITWISE_OP(const simd_view &X, \
252+
const value_type &Y) { \
253253
static_assert(std::is_integral<element_type>(), "not integral type"); \
254-
auto V2 = X.read().data() LOGIC_OP Y.data(); \
254+
auto V2 = X.read().data() BITWISE_OP Y.data(); \
255255
return simd<element_type, length>(V2); \
256256
} \
257-
ESIMD_INLINE friend auto operator LOGIC_OP(const value_type &X, \
258-
const simd_view &Y) { \
257+
ESIMD_INLINE friend auto operator BITWISE_OP(const value_type &X, \
258+
const simd_view &Y) { \
259259
static_assert(std::is_integral<element_type>(), "not integral type"); \
260-
auto V2 = X.data() LOGIC_OP Y.read().data(); \
260+
auto V2 = X.data() BITWISE_OP Y.read().data(); \
261261
return simd<element_type, length>(V2); \
262262
} \
263-
ESIMD_INLINE friend auto operator LOGIC_OP(const simd_view &X, \
264-
const simd_view &Y) { \
265-
return (X LOGIC_OP Y.read()); \
263+
ESIMD_INLINE friend auto operator BITWISE_OP(const simd_view &X, \
264+
const simd_view &Y) { \
265+
return (X BITWISE_OP Y.read()); \
266266
} \
267267
simd_view &operator OPASSIGN(const value_type &RHS) { \
268268
static_assert(std::is_integral<element_type>(), "not integeral type"); \
269-
auto V2 = read().data() LOGIC_OP RHS.data(); \
269+
auto V2 = read().data() BITWISE_OP RHS.data(); \
270270
auto V3 = convert<vector_type>(V2); \
271271
write(V3); \
272272
return *this; \
273273
} \
274274
simd_view &operator OPASSIGN(const simd_view &RHS) { \
275275
return (*this OPASSIGN RHS.read()); \
276276
}
277-
DEF_LOGIC_OP(&, &=)
278-
DEF_LOGIC_OP(|, |=)
279-
DEF_LOGIC_OP(^, ^=)
277+
DEF_BITWISE_OP(&, &=)
278+
DEF_BITWISE_OP(|, |=)
279+
DEF_BITWISE_OP(^, ^=)
280+
DEF_BITWISE_OP(>>, >>=)
281+
DEF_BITWISE_OP(<<, <<=)
282+
283+
#undef DEF_BITWISE_OP
284+
285+
#define DEF_UNARY_OP(UNARY_OP) \
286+
auto operator UNARY_OP() { \
287+
auto V = UNARY_OP(read().data()); \
288+
return simd<element_type, length>(V); \
289+
}
290+
DEF_UNARY_OP(!)
291+
DEF_UNARY_OP(~)
292+
DEF_UNARY_OP(+)
293+
DEF_UNARY_OP(-)
280294

281-
#undef DEF_LOGIC_OP
295+
#undef DEF_UNARY_OP
282296

283297
// Operator ++, --
284298
simd_view &operator++() {

‎sycl/test/esimd/simd.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,16 @@ bool test_simd_bin_ops() __attribute__((sycl_device)) {
7373
return v0[0] == 1;
7474
}
7575

76+
bool test_simd_unary_ops() __attribute__((sycl_device)) {
77+
simd<int, 8> v0 = 1;
78+
simd<int, 8> v1 = 2;
79+
v0 <<= v1;
80+
v1 = -v0;
81+
v0 = ~v1;
82+
v1 = !v0;
83+
return v1[0] == 1;
84+
}
85+
7686
bool test_nested_1d_select() __attribute__((sycl_device)) {
7787
simd<int, 8> r0(0, 1);
7888

‎sycl/test/esimd/simd_view.cpp

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,18 @@ bool test_simd_view_bin_ops() __attribute__((sycl_device)) {
3535
return v0[0] == 1;
3636
}
3737

38+
bool test_simd_view_unary_ops() __attribute__((sycl_device)) {
39+
simd<int, 16> v0 = 1;
40+
simd<int, 16> v1 = 2;
41+
auto ref0 = v0.select<8, 2>(0);
42+
auto ref1 = v1.select<8, 2>(0);
43+
ref0 <<= ref1;
44+
ref1 = -ref0;
45+
ref0 = ~ref1;
46+
ref1 = !ref0;
47+
return v1[0] == 1;
48+
}
49+
3850
bool test_simd_view_assign1() __attribute__((sycl_device)) {
3951
simd<int, 32> v0(0, 1);
4052
simd<int, 16> v1(0, 1);

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