[SYCL][FPGA] Implementing __builtin_intel_fpga_mem() #1033
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This patch creates and implements the __builtin_intel_fpga_mem builtin for
FPGA SYCL device. The builtin is used to indicate the characteristics of
the load-store unit (LSU) to be used when de-referencing the pointer.
The builtin accepts 3 arguments:
1. A pointer to a first class lvalue or to an rvalue.
2. A integer bitmask that encodes various LSU parameters. These will be
added for each language in separate libraries.
3. An integer value indicating the size of the LSU cache.
The effect of this is observable only through the FPGA hardware
generated. It lowers to an assignment in all other contexts.
Implementation strategy: In CodeGen, we generate a pointer annotation:
T* llvm.ptr.annotation.*(T*, "{params:..}{cachesize:..}", ...)
Signed-off-by: Mohammad Fawaz <[email protected]>
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erichkeane
approved these changes
Jan 22, 2020
mlychkov
approved these changes
Jan 23, 2020
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This patch creates and implements the __builtin_intel_fpga_mem builtin for
FPGA SYCL device. The builtin is used to indicate the characteristics of
the load-store unit (LSU) to be used when de-referencing the pointer.
The builtin accepts 3 arguments:
added for each language in separate libraries.
The effect of this is observable only through the FPGA hardware
generated. It lowers to an assignment in all other contexts.
Implementation strategy: In CodeGen, we generate a pointer annotation:
T* llvm.ptr.annotation.(T, "{params:..}{cachesize:..}", ...)
Signed-off-by: Mohammad Fawaz [email protected]