[Driver][SYCL][FPGA] generated dep files for AOT should be picked up …

[mdtoguchi]

…in CWD

When adding the .d files to be picked up by the aoc tool call, the generated
.d files are created in CWD when the input file is in CWD/dir/file.cpp. This
was wrong where we assumed generation was in CWD/dir

Signed-off-by: Michael D Toguchi [email protected]

[meiyacha]

…in CWD

When adding the .d files to be picked up by the aoc tool call, the generated
.d files are created in CWD when the input file is in CWD/dir/file.cpp. This
was wrong where we assumed generation was in CWD/dir

Signed-off-by: Michael D Toguchi [email protected]

Isn't the proper solution to make the .d file temporary?

[mdtoguchi]

…in CWD
When adding the .d files to be picked up by the aoc tool call, the generated
.d files are created in CWD when the input file is in CWD/dir/file.cpp. This
was wrong where we assumed generation was in CWD/dir
Signed-off-by: Michael D Toguchi [email protected]

Isn't the proper solution to make the .d file temporary?

It is the solution moving forward (and I left a comment in the code in regards to this) but I wanted to address this now at least for the next release as the fix is not as involved.

[meiyacha]

Looks good to me :)

[mdtoguchi]

@AGindinson, any input on this one?

[AGindinson]

Sorry for the late response.
The changes mostly LGTM. My only concern is: what would the behavior be if the user specified the output report destination themselves via -Xsycl-target-backend? Is this something that should be handled?

[AGindinson]

LGTM.

I'm starting to think that it would be a good idea to implement more E2E tests for the FPGA flow in the SYCL RT LIT infrastructure. This could guard us better against undesired UX issues. Coupled with a potential documentation improvement, this could make stuff easier to grasp, for our own benefit.