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[SYCL] Add PTL info to device config file #16368

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Merged
merged 4 commits into from
Dec 17, 2024
Merged

[SYCL] Add PTL info to device config file #16368

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8df6279
[SYCL] Add PTL info to device config file
jzc Dec 13, 2024
b9ddeeb
Merge remote-tracking branch 'intel/sycl' into ptl-device-config
jzc Dec 13, 2024
bae2c87
Fix typo
jzc Dec 13, 2024
de45bfd
Apply suggestions from code review
jzc Dec 16, 2024
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25 changes: 20 additions & 5 deletions llvm/include/llvm/SYCLLowerIR/DeviceConfigFile.td
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Original file line number Diff line number Diff line change
Expand Up @@ -189,11 +189,26 @@ class IntelTargetInfo<string Name, list<Aspect> Aspects, list<int> subGroupSizes
// Note: only the "canonical" target names are listed here - see
// SYCL::gen::resolveGenDevice().
//
// TODO: instructions on how to get "???" values below are required. Currently
// device architectures below which have "???" in it are not fully supported.
//
// def : IntelTargetInfo<"intel_gpu_ptl_u", ???, ???>;
// def : IntelTargetInfo<"intel_gpu_ptl_h", ???, ???>;
// When adding the new Intel architectures, the ideal way to get these
// values is to run sycl-ls --verbose on the target machine. However,
// if you don't have access to the target machine, then you can look in
// the intel/compute-runtime source code to get the values. For
// the fp64 and atomic64 aspects, look for the definition
// of specific RuntimeCapabilityTable's. These will be defined in
// a file called hw_info_<device>.cpp. For example, for PVC, it
// would be hw_info_pvc.cpp. For fp16, this is supported by all
// Intel GPUs currently. (see definition of getDeviceExtensions in
// compiler_product_helper_base.inl). For the supported sub-group sizes,
// it is not as straightforward. They are defined per family in
// GfxCoreHelperHw<Family>::getDeviceSubGroupSizes and by default
// the default sub-group sizes are 8, 16, and 32. (see gfx_core_helper_base.inl)
// However, this can be overriden by specific families. For example,
// gfx_core_helper_xe_hpc_core.cpp defines the supported sub-group
// sizes to be 16 and 32, which corresponds to PVC having 16 and 32
// as sub-group sizes the supported sub-group sizes.

def : IntelTargetInfo<"intel_gpu_ptl_u", Fp16Fp64Atomic64, Sg16_32>;
def : IntelTargetInfo<"intel_gpu_ptl_h", Fp16Fp64Atomic64, Sg16_32>;
def : IntelTargetInfo<"intel_gpu_lnl_m", Fp16Fp64Atomic64, Sg16_32>;
def : IntelTargetInfo<"intel_gpu_bmg_g21", Fp16Fp64Atomic64, Sg16_32>;
def : IntelTargetInfo<"intel_gpu_arl_h", Fp16Fp64Atomic64, Sg8_16_32>;
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