[SYCL-PTX] Add missing async and barrier builtins #1801
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| #ifndef CLC_SPIRV_BINDING | |||
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Is this file auto-generated? Should we add a comment with instructions how to modify this file?
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yes it is auto-generated,
The PR for the generator is here #1781 and it include a CMake rule to trigger the regeneration if needed. I'll add a warning header to it.
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I've made the update.
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@Naghasan, unfortunately, I don't see it.
Could you also take a look at CUDA LIT tests? They seem to hang in pre-merge checks.
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Sorry, I added it to the PR #1781 as it adds the generator. I have not regenerated the file in this PR.
Signed-off-by: Victor Lomuller <[email protected]>
Signed-off-by: Victor Lomuller <[email protected]>
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@bader I also added a lit infrastructure to libclc. It allows to make sure builtins are emitted as expected locally. |
Co-authored-by: Mariya Podchishchaeva <[email protected]>
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To avoid an empty line in autogenerated tests.
…onINTEL (intel#1801) This PR is regarding spec KhronosGroup/SPIRV-Registry#185 This patch parse the string in a "ptr.annotation" call, extracting buffer location information and create a SPIRV decoration on the pointer using the buffer location information. This applies only on the pointer argument of OpLoad/Opstore Original commit: KhronosGroup/SPIRV-LLVM-Translator@9ccf154
Add missing async and barrier builtins.
Update the forward declaration to be in sync with the SPIRVBuiltins.td
Signed-off-by: Victor Lomuller [email protected]