[SYCL][ESIMD] Prepare LLVM IR for OS spirv translator

clang/lib/CodeGen/BackendUtil.cpp

@@ -27,6 +27,7 @@
 #include "llvm/CodeGen/RegAllocRegistry.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/IRPrintingPasses.h"
 #include "llvm/IR/LegacyPassManager.h"
@@ -890,6 +891,9 @@ void EmitAssemblyHelper::EmitAssembly(BackendAction Action,
   if (LangOpts.SYCLIsDevice && CodeGenOpts.DisableLLVMPasses)
     PerModulePasses.add(createDeadCodeEliminationPass());
 
+  if (LangOpts.SYCLIsDevice && LangOpts.SYCLExplicitSIMD)
+    PerModulePasses.add(createGenXSPIRVWriterAdaptorPass());
+
   switch (Action) {
   case Backend_EmitNothing:
     break;

clang/lib/CodeGen/CMakeLists.txt

@@ -31,6 +31,13 @@ if (MSVC)
   set_source_files_properties(CodeGenModule.cpp PROPERTIES COMPILE_FLAGS /bigobj)
 endif()
 
+get_property(LLVMGenXIntrinsics_SOURCE_DIR GLOBAL PROPERTY LLVMGenXIntrinsics_SOURCE_PROP)
+get_property(LLVMGenXIntrinsics_BINARY_DIR GLOBAL PROPERTY LLVMGenXIntrinsics_BINARY_PROP)
+
+include_directories(
+  ${LLVMGenXIntrinsics_SOURCE_DIR}/GenXIntrinsics/include
+  ${LLVMGenXIntrinsics_BINARY_DIR}/GenXIntrinsics/include)
+
 add_clang_library(clangCodeGen
   BackendUtil.cpp
   CGAtomic.cpp
@@ -91,8 +98,14 @@ add_clang_library(clangCodeGen
   TargetInfo.cpp
   VarBypassDetector.cpp
 
+  ADDITIONAL_HEADER_DIRS
+  ${LLVMGenXIntrinsics_SOURCE_DIR}/GenXIntrinsics/include
+  ${LLVMGenXIntrinsics_BINARY_DIR}/GenXIntrinsics/include
+
   DEPENDS
+  ${codegen_deps}
   intrinsics_gen
+  LLVMGenXIntrinsics
 
   LINK_LIBS
   clangAnalysis
@@ -102,4 +115,5 @@ add_clang_library(clangCodeGen
   clangFrontend
   clangLex
   clangSerialization
+  LLVMGenXIntrinsics
   )

clang/lib/CodeGen/CodeGenModule.cpp

@@ -641,12 +641,12 @@ void CodeGenModule::Release() {
     SPIRVerMD->addOperand(llvm::MDNode::get(Ctx, SPIRVerElts));
     // We are trying to look like OpenCL C++ for SPIR-V translator.
     // 4 - OpenCL_CPP, 100000 - OpenCL C++ version 1.0
-    // 6 - ESIMD, if any kernel or function is an explicit SIMD one
+    // 0 - ESIMD, if any kernel or function is an explicit SIMD one
     int Lang = llvm::any_of(TheModule,
                             [](const auto &F) {
                               return F.getMetadata("sycl_explicit_simd");
                             })
-                   ? 6
+                   ? 0
                    : 4;
 
     llvm::Metadata *SPIRVSourceElts[] = {

clang/lib/Driver/ToolChains/Clang.cpp

@@ -7658,6 +7658,8 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA,
   if (getToolChain().getTriple().isSYCLDeviceEnvironment()) {
     TranslatorArgs.push_back("-spirv-max-version=1.1");
     std::string ExtArg("-spirv-ext=+all");
+    if (C.getArgs().hasArg(options::OPT_fsycl_esimd))
+      TranslatorArgs.push_back("-spirv-allow-unknown-intrinsics");
     // Disable SPV_INTEL_usm_storage_classes by default since it adds new
     // storage classes that represent global_device and global_host address
     // spaces, which are not supported for all targets. With the extension

clang/lib/Driver/ToolChains/SYCL.cpp

@@ -42,6 +42,8 @@ const char *SYCL::Linker::constructLLVMSpirvCommand(Compilation &C,
   } else {
     CmdArgs.push_back("-spirv-max-version=1.1");
     CmdArgs.push_back("-spirv-ext=+all");
+    if (C.getArgs().hasArg(options::OPT_fsycl_esimd))
+      CmdArgs.push_back("-spirv-allow-unknown-intrinsics");
     CmdArgs.push_back("-o");
     CmdArgs.push_back(Output.getFilename());
   }

clang/test/CodeGenSYCL/esimd-private-global.cpp

@@ -11,4 +11,4 @@ SYCL_EXTERNAL void init_vc(int x) {
   vc = x;
   // CHECK: store i32 %0, i32* @vc
 }
-// CHECK: attributes #0 = { "genx_byte_offset"="17" "genx_volatile" }
+// CHECK: attributes #0 = {{.*"VCByteOffset"="17".*"VCVolatile"}}

clang/test/CodeGenSYCL/esimd_metadata1.cpp

@@ -19,6 +19,6 @@ void bar() {
 }
 
 // CHECK: !spirv.Source = !{[[LANG:![0-9]+]]}
-// CHECK: [[LANG]] = !{i32 6, i32 100000}
+// CHECK: [[LANG]] = !{i32 0, i32 {{[0-9]+}}}
 // CHECK: ![[EMPTY]] = !{}
 // CHECK: ![[REQD_SIZE]] = !{i32 1}

clang/test/CodeGenSYCL/esimd_metadata2.cpp

@@ -35,5 +35,5 @@ void bar() {
 }
 
 // CHECK: !spirv.Source = !{[[LANG:![0-9]+]]}
-// CHECK: [[LANG]] = !{i32 6, i32 100000}
+// CHECK: [[LANG]] = !{i32 0, i32 {{[0-9]+}}}
 // CHECK-ESIMD: ![[SGSIZE1]] = !{i32 1}

clang/test/Driver/sycl-offload.c

@@ -593,6 +593,10 @@
 // CHECK-LINK-SYCL-DEBUG: "{{.*}}link{{(.exe)?}}"
 // CHECK-LINK-SYCL-DEBUG: "-defaultlib:sycld.lib"
 
+/// Check "-spirv-allow-unknown-intrinsics" option is emitted for llvm-spirv tool for esimd mode
+// RUN: %clangxx %s -fsycl -fsycl-explicit-simd -### 2>&1 | FileCheck %s --check-prefix=CHK-FSYCL-ESIMD
+// CHK-FSYCL-ESIMD: llvm-spirv{{.*}}-spirv-allow-unknown-intrinsics
+
 /// ###########################################################################
 
 /// Check -Xsycl-target-backend triggers error when multiple triples are used.

llvm/lib/SYCLLowerIR/CMakeLists.txt

@@ -7,7 +7,7 @@ if (NOT TARGET LLVMGenXIntrinsics)
     include(FetchContent)
     FetchContent_Declare(vc-intrinsics
       GIT_REPOSITORY https://github.com/intel/vc-intrinsics.git
-      GIT_TAG        cce6e48c28eb850d7dadd30841c0d95f009bbca1
+      GIT_TAG        5e35898100ebe3747ea50c91b05e679757b25703
     )
     FetchContent_MakeAvailable(vc-intrinsics)
     FetchContent_GetProperties(vc-intrinsics)
@@ -28,6 +28,9 @@ if (NOT TARGET LLVMGenXIntrinsics)
   )
 endif()
 
+set_property(GLOBAL PROPERTY LLVMGenXIntrinsics_SOURCE_PROP ${LLVMGenXIntrinsics_SOURCE_DIR})
+set_property(GLOBAL PROPERTY LLVMGenXIntrinsics_BINARY_PROP ${LLVMGenXIntrinsics_BINARY_DIR})
+
 add_llvm_component_library(LLVMSYCLLowerIR
   LowerWGScope.cpp
   LowerESIMD.cpp