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[SYCL][FPGA] Enable USM address spaces by default for the hardware #2379

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Merged
merged 5 commits into from
Aug 31, 2020
Merged

[SYCL][FPGA] Enable USM address spaces by default for the hardware #2379

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6fb9973
[SYCL][FPGA] Enable USM address spaces by default for the hardware
MrSidims Aug 27, 2020
c99786f
Resolve clang-format concerns
MrSidims Aug 27, 2020
0673272
Simulation -> simulator
MrSidims Aug 28, 2020
47d8ab9
Add negative test
MrSidims Aug 28, 2020
82b5d1d
Revert "Simulation -> simulator"
MrSidims Aug 31, 2020
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3 changes: 0 additions & 3 deletions clang/include/clang/Driver/Options.td
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Expand Up @@ -1866,9 +1866,6 @@ def fstrict_vtable_pointers: Flag<["-"], "fstrict-vtable-pointers">,
def fstrict_overflow : Flag<["-"], "fstrict-overflow">, Group<f_Group>;
def fintelfpga : Flag<["-"], "fintelfpga">, Group<f_Group>,
Flags<[CC1Option, CoreOption]>, HelpText<"Perform ahead of time compilation for FPGA">;
def fsycl_enable_usm_address_spaces : Flag<["-"], "fsycl-enable-usm-address-spaces">,
Group<f_Group>, Flags<[CC1Option, CoreOption]>,
HelpText<"Enable USM address spaces">;
def fsycl_device_only : Flag<["-"], "fsycl-device-only">, Flags<[CoreOption]>,
HelpText<"Compile SYCL kernels for device">;
def fsycl_targets_EQ : CommaJoined<["-"], "fsycl-targets=">, Flags<[DriverOption, CC1Option, CoreOption]>,
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26 changes: 17 additions & 9 deletions clang/lib/Driver/ToolChains/Clang.cpp
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Expand Up @@ -6241,11 +6241,10 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
if (Args.hasArg(options::OPT_fsycl_unnamed_lambda))
CmdArgs.push_back("-fsycl-unnamed-lambda");

// Enable generation of USM address spaces as opt-in.
// Enable generation of USM address spaces for FPGA.
// __ENABLE_USM_ADDR_SPACE__ will be used during compilation of SYCL headers
if (getToolChain().getTriple().getSubArch() ==
llvm::Triple::SPIRSubArch_fpga &&
Args.hasArg(options::OPT_fsycl_enable_usm_address_spaces))
llvm::Triple::SPIRSubArch_fpga)
CmdArgs.push_back("-D__ENABLE_USM_ADDR_SPACE__");
}

Expand Down Expand Up @@ -7699,18 +7698,27 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA,
TranslatorArgs.push_back(Output.getFilename());
if (getToolChain().getTriple().isSYCLDeviceEnvironment()) {
TranslatorArgs.push_back("-spirv-max-version=1.1");
std::string ExtArg("-spirv-ext=+all");
if (C.getArgs().hasArg(options::OPT_fsycl_esimd))
TranslatorArgs.push_back("-spirv-allow-unknown-intrinsics");

// Disable SPV_INTEL_usm_storage_classes by default since it adds new
// storage classes that represent global_device and global_host address
// spaces, which are not supported for all targets. With the extension
// disable the storage classes will be lowered to CrossWorkgroup storage
// class that is mapped to just global address space.
if (!(getToolChain().getTriple().getSubArch() ==
llvm::Triple::SPIRSubArch_fpga &&
TCArgs.hasArg(options::OPT_fsycl_enable_usm_address_spaces)))
ExtArg += ",-SPV_INTEL_usm_storage_classes";
// class that is mapped to just global address space. The extension is
// supposed to be enabled only for FPGA hardware.
std::string ExtArg("-spirv-ext=+all,-SPV_INTEL_usm_storage_classes");
if (getToolChain().getTriple().getSubArch() ==
llvm::Triple::SPIRSubArch_fpga) {
for (auto *A : TCArgs) {
if (A->getOption().matches(options::OPT_Xs_separate) ||
A->getOption().matches(options::OPT_Xs)) {
StringRef ArgString(A->getValue());
if (ArgString == "hardware" || ArgString == "simulation")
ExtArg = "-spirv-ext=+all";
}
}
}
TranslatorArgs.push_back(TCArgs.MakeArgString(ExtArg));
}
for (auto I : Inputs) {
Expand Down
2 changes: 1 addition & 1 deletion clang/test/Driver/sycl-offload-with-split.c
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Expand Up @@ -217,7 +217,7 @@
// CHK-TOOLS-GEN: clang-offload-wrapper{{.*}} "-o=[[OUTPUT8:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_gen" "-kind=sycl" "-batch" "[[OUTPUT7]]"
// CHK-TOOLS-CPU: clang-offload-wrapper{{.*}} "-o=[[OUTPUT8:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_x86_64" "-kind=sycl" "-batch" "[[OUTPUT7]]"
// CHK-TOOLS-AOT: llc{{.*}} "-filetype=obj" "-o" "[[OUTPUT9:.+\.o]]" "[[OUTPUT8]]"
// CHK-TOOLS-FPGA: clang{{.*}} "-triple" "spir64_fpga-unknown-unknown-sycldevice" {{.*}} "-fsycl-int-header=[[INPUT1:.+\.h]]" "-faddrsig"
// CHK-TOOLS-FPGA: clang{{.*}} "-triple" "spir64_fpga-unknown-unknown-sycldevice" {{.*}} "-fsycl-int-header=[[INPUT1:.+\.h]]" "-D__ENABLE_USM_ADDR_SPACE__" "-faddrsig"
// CHK-TOOLS-GEN: clang{{.*}} "-triple" "spir64_gen-unknown-unknown-sycldevice" {{.*}} "-fsycl-int-header=[[INPUT1:.+\.h]]" "-faddrsig"
// CHK-TOOLS-CPU: clang{{.*}} "-triple" "spir64_x86_64-unknown-unknown-sycldevice" {{.*}} "-fsycl-int-header=[[INPUT1:.+\.h]]" "-faddrsig"
// CHK-TOOLS-AOT: clang{{.*}} "-triple" "x86_64-unknown-linux-gnu" {{.*}} "-include" "[[INPUT1]]" {{.*}} "-o" "[[OUTPUT10:.+\.o]]"
Expand Down
19 changes: 13 additions & 6 deletions clang/test/Driver/sycl-offload.c
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Expand Up @@ -646,13 +646,21 @@
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-DISABLE
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga %s -### 2>&1 \
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-DISABLE
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -fsycl-enable-usm-address-spaces %s -### 2>&1 \
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -Xshardware %s -### 2>&1 \
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -fsycl-enable-usm-address-spaces %s -### 2>&1 \
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -Xshardware %s -### 2>&1 \
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice -fsycl-enable-usm-address-spaces %s -### 2>&1 \
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -Xssimulation %s -### 2>&1 \
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -Xssimulation %s -### 2>&1 \
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -Xsemulator %s -### 2>&1 \
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-DISABLE
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -Xsemulator %s -### 2>&1 \
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-DISABLE
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice %s -### 2>&1 \
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-GEN
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice -fsycl-enable-usm-address-spaces %s -### 2>&1 \
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice %s -### 2>&1 \
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-CPU
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice %s -### 2>&1 \
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-GEN
Expand All @@ -672,8 +680,7 @@
// CHK-TOOLS-GEN: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_gen{{.*}}" "-kind=sycl" "[[OUTPUT4]]"
// CHK-TOOLS-CPU: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_x86_64{{.*}}" "-kind=sycl" "[[OUTPUT4]]"
// CHK-TOOLS-AOT: llc{{.*}} "-filetype=obj" "-o" "[[OUTPUT6:.+\.o]]" "[[OUTPUT5]]"
// CHK-TOOLS-FPGA-USM-DISABLE: clang{{.*}} "-triple" "spir64_fpga-unknown-unknown-sycldevice" {{.*}} "-fsycl-int-header=[[INPUT1:.+\.h]]" "-faddrsig"
// CHK-TOOLS-FPGA-USM-ENABLE: clang{{.*}} "-triple" "spir64_fpga-unknown-unknown-sycldevice" {{.*}} "-fsycl-int-header=[[INPUT1:.+\.h]]" "-D__ENABLE_USM_ADDR_SPACE__" "-faddrsig"
// CHK-TOOLS-FPGA: clang{{.*}} "-triple" "spir64_fpga-unknown-unknown-sycldevice" {{.*}} "-fsycl-int-header=[[INPUT1:.+\.h]]" "-D__ENABLE_USM_ADDR_SPACE__" "-faddrsig"
// CHK-TOOLS-GEN: clang{{.*}} "-triple" "spir64_gen-unknown-unknown-sycldevice" {{.*}} "-fsycl-int-header=[[INPUT1:.+\.h]]" "-faddrsig"
// CHK-TOOLS-CPU: clang{{.*}} "-triple" "spir64_x86_64-unknown-unknown-sycldevice" {{.*}} "-fsycl-int-header=[[INPUT1:.+\.h]]" "-faddrsig"
// CHK-TOOLS-AOT: clang{{.*}} "-triple" "x86_64-unknown-linux-gnu" {{.*}} "-include" "[[INPUT1]]" {{.*}} "-o" "[[OUTPUT7:.+\.o]]"
Expand Down