[SYCL] Add code examples for all SYCL FPGA loop attributes

[smanna12]

This is a follow-up in #2715 (comment)

This patch improves the documentation by adding code examples for all FPGA loop
attributes that we did not have before.

Signed-off-by: Soumi Manna [email protected]

[MrSidims]

May be it would be valuable to also add an example like this:

template<int N>
void bar() {
  [[intel::loop_attr(N)]] for(;;) { }
}

[smanna12]

May be it would be valuable to also add an example like this:

template<int N>
void bar() {
  [[intel::loop_attr(N)]] for(;;) { }
}

@MrSidims Thanks for looking into this. Yes, i agree with you that it would be valuable to add template examples. I have updated doc with the template exmaples.