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[SYCL] Add an attr tablegen feature for checking langopts #3234

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merged 5 commits into from
Feb 25, 2021
Merged

[SYCL] Add an attr tablegen feature for checking langopts #3234

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5a6e060
Add an attr tablegen feature for checking langopts
AaronBallman Feb 19, 2021
5110b41
Slight redesign of the feature.
AaronBallman Feb 22, 2021
7572651
Update the statement attribute definitions; NFC.
AaronBallman Feb 22, 2021
d4994cb
Renaming the tablegen option based on offline discussion; NFC
AaronBallman Feb 22, 2021
95ee4e6
Merge remote-tracking branch 'upstream/sycl' into host-device-attr-la…
AaronBallman Feb 23, 2021
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51 changes: 28 additions & 23 deletions clang/include/clang/Basic/Attr.td
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Original file line number Diff line number Diff line change
Expand Up @@ -317,10 +317,14 @@ class SubjectList<list<AttrSubject> subjects, SubjectDiag diag = WarnDiag,
string CustomDiag = customDiag;
}

class LangOpt<string name, code customCode = [{}]> {
class LangOpt<string name, code customCode = [{}], bit silentlyIgnore = 0> {
// The language option to test; ignored when custom code is supplied.
string Name = name;

// If set to 1, the attribute is accepted but is silently ignored. This is
// useful in multi-compilation situations like SYCL.
bit SilentlyIgnore = silentlyIgnore;

// A custom predicate, written as an expression evaluated in a context with
// "LangOpts" bound.
code CustomCode = customCode;
Expand All @@ -329,9 +333,10 @@ def MicrosoftExt : LangOpt<"MicrosoftExt">;
def Borland : LangOpt<"Borland">;
def CUDA : LangOpt<"CUDA">;
def HIP : LangOpt<"HIP">;
def SYCL : LangOpt<"SYCL">;
def SYCLIsDevice : LangOpt<"SYCLIsDevice">;
def SYCL : LangOpt<"SYCLIsDevice">;
def SYCLIsHost : LangOpt<"SYCLIsHost">;
def SilentlyIgnoreSYCLIsHost : LangOpt<"SYCLIsHost", "", 1>;
def SYCLExplicitSIMD : LangOpt<"SYCLExplicitSIMD">;
def COnly : LangOpt<"", "!LangOpts.CPlusPlus">;
def CPlusPlus : LangOpt<"CPlusPlus">;
Expand Down Expand Up @@ -1322,7 +1327,7 @@ def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
let Spellings = [CXX11<"intelfpga","no_global_work_offset">,
CXX11<"intel","no_global_work_offset">];
let Args = [ExprArgument<"Value", /*optional*/1>];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Subjects = SubjectList<[Function], ErrorDiag>;
let Documentation = [SYCLIntelNoGlobalWorkOffsetAttrDocs];
}
Expand All @@ -1331,7 +1336,7 @@ def SYCLIntelLoopFuse : InheritableAttr {
let Spellings = [CXX11<"intel", "loop_fuse">,
CXX11<"intel", "loop_fuse_independent">];
let Args = [ExprArgument<"Value", /*optional=*/ 1>];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Subjects = SubjectList<[Function], ErrorDiag>;
let Accessors = [Accessor<"isIndependent",
[CXX11<"intel", "loop_fuse_independent">]>];
Expand Down Expand Up @@ -1395,7 +1400,7 @@ def IntelReqdSubGroupSize: InheritableAttr {
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[Function], ErrorDiag>;
let Documentation = [IntelReqdSubGroupSizeDocs];
let LangOpts = [OpenCL, SYCLIsDevice, SYCLIsHost];
let LangOpts = [OpenCL, SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
}

// This attribute is both a type attribute, and a declaration attribute (for
Expand Down Expand Up @@ -1841,7 +1846,7 @@ def SYCLIntelFPGAInitiationInterval : StmtAttr {
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let Args = [ExprArgument<"IntervalExpr">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let HasCustomTypeTransform = 1;
let Documentation = [SYCLIntelFPGAInitiationIntervalAttrDocs];
}
Expand All @@ -1852,7 +1857,7 @@ def SYCLIntelFPGAMaxConcurrency : StmtAttr {
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let Args = [ExprArgument<"NThreadsExpr">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let HasCustomTypeTransform = 1;
let Documentation = [SYCLIntelFPGAMaxConcurrencyAttrDocs];
}
Expand All @@ -1863,7 +1868,7 @@ def SYCLIntelFPGALoopCoalesce : StmtAttr {
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let Args = [ExprArgument<"NExpr">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let HasCustomTypeTransform = 1;
let Documentation = [SYCLIntelFPGALoopCoalesceAttrDocs];
}
Expand All @@ -1873,7 +1878,7 @@ def SYCLIntelFPGADisableLoopPipelining : StmtAttr {
CXX11<"intel","disable_loop_pipelining">];
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let HasCustomTypeTransform = 1;
let Documentation = [SYCLIntelFPGADisableLoopPipeliningAttrDocs];
}
Expand All @@ -1884,7 +1889,7 @@ def SYCLIntelFPGAMaxInterleaving : StmtAttr {
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let Args = [ExprArgument<"NExpr">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let HasCustomTypeTransform = 1;
let Documentation = [SYCLIntelFPGAMaxInterleavingAttrDocs];
}
Expand All @@ -1895,7 +1900,7 @@ def SYCLIntelFPGASpeculatedIterations : StmtAttr {
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let Args = [ExprArgument<"NExpr">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let HasCustomTypeTransform = 1;
let Documentation = [SYCLIntelFPGASpeculatedIterationsAttrDocs];
}
Expand All @@ -1904,7 +1909,7 @@ def SYCLIntelFPGANofusion : StmtAttr {
let Spellings = [CXX11<"intel","nofusion">];
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let HasCustomTypeTransform = 1;
let Documentation = [SYCLIntelFPGANofusionAttrDocs];
}
Expand Down Expand Up @@ -1946,7 +1951,7 @@ def IntelFPGADoublePump : Attr {
CXX11<"intel", "doublepump">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [IntelFPGADoublePumpAttrDocs];
}

Expand All @@ -1955,7 +1960,7 @@ def IntelFPGASinglePump : Attr {
CXX11<"intel", "singlepump">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [IntelFPGASinglePumpAttrDocs];
}

Expand All @@ -1976,7 +1981,7 @@ def IntelFPGAMemory : Attr {
}];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [IntelFPGAMemoryAttrDocs];
}

Expand All @@ -1985,7 +1990,7 @@ def IntelFPGARegister : Attr {
CXX11<"intel", "fpga_register">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [IntelFPGARegisterAttrDocs];
}

Expand All @@ -1996,7 +2001,7 @@ def IntelFPGABankWidth : Attr {
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [IntelFPGABankWidthAttrDocs];
}

Expand All @@ -2006,15 +2011,15 @@ def IntelFPGANumBanks : Attr {
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [IntelFPGANumBanksAttrDocs];
}

def IntelFPGAPrivateCopies : InheritableAttr {
let Spellings = [CXX11<"intelfpga","private_copies">,
CXX11<"intel","private_copies">];
let Args = [ExprArgument<"Value">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
let Documentation = [IntelFPGAPrivateCopiesAttrDocs];
}
Expand All @@ -2026,7 +2031,7 @@ def IntelFPGAMerge : Attr {
let Args = [StringArgument<"Name">, StringArgument<"Direction">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [IntelFPGAMergeAttrDocs];
}

Expand All @@ -2036,7 +2041,7 @@ def IntelFPGAMaxReplicates : Attr {
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [IntelFPGAMaxReplicatesAttrDocs];
}

Expand All @@ -2045,7 +2050,7 @@ def IntelFPGASimpleDualPort : Attr {
CXX11<"intel","simple_dual_port">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [IntelFPGASimpleDualPortAttrDocs];
}

Expand Down Expand Up @@ -2081,7 +2086,7 @@ def IntelFPGAForcePow2Depth : Attr {
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [IntelFPGAForcePow2DepthAttrDocs];
let AdditionalMembers = [{
static unsigned getMinValue() {
Expand Down
40 changes: 0 additions & 40 deletions clang/lib/Sema/SemaDeclAttr.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3211,9 +3211,6 @@ static void handleWorkGroupSizeHint(Sema &S, Decl *D, const ParsedAttr &AL) {

void Sema::AddIntelReqdSubGroupSize(Decl *D, const AttributeCommonInfo &CI,
Expr *E) {
if (LangOpts.SYCLIsHost)
return;

if (!E->isValueDependent()) {
// Validate that we have an integer constant expression and then store the
// converted constant expression into the semantic attribute so that we
Expand Down Expand Up @@ -3470,10 +3467,6 @@ void Sema::addSYCLIntelLoopFuseAttr(Decl *D, const AttributeCommonInfo &CI,
if (checkSYCLIntelLoopFuseArgument(*this, CI, E))
return;

// Attribute should not be added during host compilation.
if (getLangOpts().SYCLIsHost)
return;

SYCLIntelLoopFuseAttr *NewAttr = mergeSYCLIntelLoopFuseAttr(D, CI, E);

if (NewAttr)
Expand Down Expand Up @@ -5717,9 +5710,6 @@ static bool checkForDuplicateAttribute(Sema &S, Decl *D,

static void handleNoGlobalWorkOffsetAttr(Sema &S, Decl *D,
const ParsedAttr &A) {
if (S.LangOpts.SYCLIsHost)
return;

checkForDuplicateAttribute<SYCLIntelNoGlobalWorkOffsetAttr>(S, D, A);
S.CheckDeprecatedSYCLAttributeSpelling(A);

Expand All @@ -5736,9 +5726,6 @@ static void handleNoGlobalWorkOffsetAttr(Sema &S, Decl *D,
/// Both are incompatible with the __register__ attribute.
template <typename AttrType, typename IncompatAttrType>
static void handleIntelFPGAPumpAttr(Sema &S, Decl *D, const ParsedAttr &A) {
if (S.LangOpts.SYCLIsHost)
return;

checkForDuplicateAttribute<AttrType>(S, D, A);
if (checkAttrMutualExclusion<IncompatAttrType>(S, D, A))
return;
Expand All @@ -5759,10 +5746,6 @@ static void handleIntelFPGAPumpAttr(Sema &S, Decl *D, const ParsedAttr &A) {
/// This is incompatible with the [[intelfpga::register]] attribute.
static void handleIntelFPGAMemoryAttr(Sema &S, Decl *D,
const ParsedAttr &AL) {

if (S.LangOpts.SYCLIsHost)
return;

checkForDuplicateAttribute<IntelFPGAMemoryAttr>(S, D, AL);
if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, AL))
return;
Expand Down Expand Up @@ -5832,10 +5815,6 @@ static bool checkIntelFPGARegisterAttrCompatibility(Sema &S, Decl *D,
/// Handle the [[intelfpga::register]] attribute.
/// This is incompatible with most of the other memory attributes.
static void handleIntelFPGARegisterAttr(Sema &S, Decl *D, const ParsedAttr &A) {

if (S.LangOpts.SYCLIsHost)
return;

checkForDuplicateAttribute<IntelFPGARegisterAttr>(S, D, A);
if (checkIntelFPGARegisterAttrCompatibility(S, D, A))
return;
Expand All @@ -5853,10 +5832,6 @@ static void handleIntelFPGARegisterAttr(Sema &S, Decl *D, const ParsedAttr &A) {
template <typename AttrType>
static void handleOneConstantPowerTwoValueAttr(Sema &S, Decl *D,
const ParsedAttr &A) {

if (S.LangOpts.SYCLIsHost)
return;

checkForDuplicateAttribute<AttrType>(S, D, A);
if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, A))
return;
Expand All @@ -5868,9 +5843,6 @@ static void handleOneConstantPowerTwoValueAttr(Sema &S, Decl *D,

static void handleIntelFPGASimpleDualPortAttr(Sema &S, Decl *D,
const ParsedAttr &AL) {
if (S.LangOpts.SYCLIsHost)
return;

checkForDuplicateAttribute<IntelFPGASimpleDualPortAttr>(S, D, AL);

if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, AL))
Expand All @@ -5888,9 +5860,6 @@ static void handleIntelFPGASimpleDualPortAttr(Sema &S, Decl *D,

static void handleIntelFPGAMaxReplicatesAttr(Sema &S, Decl *D,
const ParsedAttr &A) {
if (S.LangOpts.SYCLIsHost)
return;

checkForDuplicateAttribute<IntelFPGAMaxReplicatesAttr>(S, D, A);

if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, A))
Expand All @@ -5908,9 +5877,6 @@ static void handleIntelFPGAMaxReplicatesAttr(Sema &S, Decl *D,
static void handleIntelFPGAMergeAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
checkForDuplicateAttribute<IntelFPGAMergeAttr>(S, D, AL);

if (S.LangOpts.SYCLIsHost)
return;

if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, AL))
return;

Expand Down Expand Up @@ -6029,9 +5995,6 @@ void Sema::AddIntelFPGABankBitsAttr(Decl *D, const AttributeCommonInfo &CI,

static void handleIntelFPGAPrivateCopiesAttr(Sema &S, Decl *D,
const ParsedAttr &A) {
if (S.LangOpts.SYCLIsHost)
return;

checkForDuplicateAttribute<IntelFPGAPrivateCopiesAttr>(S, D, A);
if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, A))
return;
Expand All @@ -6043,9 +6006,6 @@ static void handleIntelFPGAPrivateCopiesAttr(Sema &S, Decl *D,

static void handleIntelFPGAForcePow2DepthAttr(Sema &S, Decl *D,
const ParsedAttr &A) {
if (S.LangOpts.SYCLIsHost)
return;

checkForDuplicateAttribute<IntelFPGAForcePow2DepthAttr>(S, D, A);

if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, A))
Expand Down
6 changes: 0 additions & 6 deletions clang/test/CodeGenSYCL/loop_fusion_host.cpp
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Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@
// RUN: %clang_cc1 -fsycl -fsycl-is-host -triple -x86_64-unknown-linux-gnu -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -fsycl -fsycl-is-host -triple -x86_64-unknown-linux-gnu -disable-llvm-passes -verify -Wno-sycl-2017-compat -DDIAG %s

template <typename name, typename Func>
__attribute__((sycl_kernel)) void kernel(const Func &kernelFunc) {
Expand Down Expand Up @@ -30,8 +29,3 @@ void foo() {
kernel<class kernel_name_1>(f5);
}
// CHECK-NOT: !loop_fuse

#if defined(DIAG)
int baz();
[[intel::loop_fuse(baz())]] void func3(); // expected-error{{'loop_fuse' attribute requires an integer constant}}
#endif
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