[SYCL][L0] Programming guide for multi-tile and multi-card under Level-Zero backend. #3872
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vladimirlaz
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Jun 3, 2021
alexbatashev
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@smaslov-intel could you please update index.rst file in the same directory? It is required for correct rendering to https://intel.github.io/llvm-docs/
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…l-Zero backend. Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
pvchupin
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Jun 3, 2021
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
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Have no idea why CI is broken:
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@tfzhu, one more issue |
Same as for other PRs restart helped. |
pvchupin
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vladimirlaz
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alexbatashev
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Signed-off-by: Sergey V Maslov [email protected]