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[Driver][FPGA][SYCL] Add specific timing diagnostic for FPGA AOT #3965
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There are cases in which the generation of FPGA device code from 'aoc' is known to have timing issues. Add a specific diagnostic from the driver when this case is encountered. A special return code (42) is used to inform the driver of this situation. Additionally in this situation, we also want to allow for the compilation to continue so the user can use the generated binary knowing the timing issue as stated.
Only |
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The approach LGTM overall, just a couple stylistic comments
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llvm-foreach
part LGTM. However, it would be great to have a test for error code preserving mechanism
Use separate DenseMap for exit behaviors Update names and usage model to avoid double negatives
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LGTM.
@AlexeySachkov, can you take another look? |
@bader, can this be merged without |
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llvm-foreach
changes look good to me, but one comment update seems to be unintentional. Right?
There are cases in which the generation of FPGA device code from 'aoc'
is known to have timing issues. Add a specific diagnostic from the
driver when this case is encountered. A special return code (42) is
used to inform the driver of this situation.
Additionally in this situation, we also want to allow for the compilation
to continue so the user can use the generated binary knowing the timing
issue as stated.