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[SYCL] Enable SPV_INTEL_runtime_aligned for FPGA only #5299

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Jan 14, 2022
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13 changes: 4 additions & 9 deletions clang/lib/Driver/ToolChains/Clang.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -9041,17 +9041,12 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA,
",+SPV_INTEL_long_constant_composite"
",+SPV_INTEL_fpga_invocation_pipelining_attributes"
",+SPV_INTEL_fpga_dsp_control"
",+SPV_INTEL_arithmetic_fence"
",+SPV_INTEL_runtime_aligned";
",+SPV_INTEL_arithmetic_fence";
ExtArg = ExtArg + DefaultExtArg + INTELExtArg;
if (!C.getDriver().isFPGAEmulationMode())
// Enable SPV_INTEL_usm_storage_classes only for FPGA hardware,
// since it adds new storage classes that represent global_device and
// global_host address spaces, which are not supported for all
// targets. With the extension disabled the storage classes will be
// lowered to CrossWorkgroup storage class that is mapped to just
// global address space.
ExtArg += ",+SPV_INTEL_usm_storage_classes";
// Enable several extensions on FPGA H/W exclusively
ExtArg += ",+SPV_INTEL_usm_storage_classes"
",+SPV_INTEL_runtime_aligned";
else
// Don't enable several freshly added extensions on FPGA H/W
ExtArg += ",+SPV_INTEL_token_type"
Expand Down
5 changes: 2 additions & 3 deletions clang/test/Driver/sycl-spirv-ext.c
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,6 @@
// CHECK-DEFAULT-SAME:,+SPV_INTEL_fpga_invocation_pipelining_attributes
// CHECK-DEFAULT-SAME:,+SPV_INTEL_fpga_dsp_control
// CHECK-DEFAULT-SAME:,+SPV_INTEL_arithmetic_fence
// CHECK-DEFAULT-SAME:,+SPV_INTEL_runtime_aligned
// CHECK-DEFAULT-SAME:,+SPV_INTEL_token_type
// CHECK-DEFAULT-SAME:,+SPV_INTEL_bfloat16_conversion
// CHECK-DEFAULT-SAME:,+SPV_INTEL_joint_matrix
Expand Down Expand Up @@ -80,5 +79,5 @@
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_fpga_invocation_pipelining_attributes
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_fpga_dsp_control
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_arithmetic_fence
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_runtime_aligned
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_usm_storage_classes"
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_usm_storage_classes
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_runtime_aligned"