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[SYCL][DOC] Move proposed FPGA extensions #5453

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Feb 4, 2022
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[SYCL][DOC] Move proposed FPGA extensions #5453

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[SYCL][DOC] Move proposed FPGA extensions
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6 changes: 5 additions & 1 deletion ...es/data_flow_pipes_rev4_proposed.asciidoc → ...ed/SYCL_EXT_INTEL_DATAFLOW_PIPES.asciidoc
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:language: {basebackend@docbook:c++:cpp}

== Introduction
IMPORTANT: This specification is a draft.
IMPORTANT: This is a proposed update to an existing extension. The APIs
described in this document are not yet implemented and cannot be used in
application code. See
link:../supported/SYCL_EXT_INTEL_DATAFLOW_PIPES.asciidoc[here] for the existing
extension, which is implemented.

NOTE: Khronos(R) is a registered trademark and SYCL(TM) and SPIR(TM) are trademarks of The Khronos Group Inc. OpenCL(TM) is a trademark of Apple Inc. used by permission by Khronos.

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7 changes: 7 additions & 0 deletions ...nsions/IntelFPGA/FPGALsu_rev2_proposed.md → ...sions/proposed/SYCL_EXT_INTEL_FPGA_LSU.md
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# FPGA lsu

**IMPORTANT:** This is a proposed update to an existing extension. The APIs
described in this document are not yet implemented and cannot be used in
application code. See [here][1] for the existing extension, which is
implemented.

[1]: <../supported/SYCL_EXT_INTEL_FPGA_LSU.md>

The Intel FPGA `lsu` class is implemented in `sycl/ext/intel/fpga_lsu.hpp` which
is included in `sycl/ext/intel/fpga_extensions.hpp`.

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