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[SYCL][FPGA] Expose value_type and min_capacity from SYCL pipes extension class #5471

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Merged
merged 9 commits into from
Mar 3, 2022

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tyoungsc
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@tyoungsc tyoungsc commented Feb 3, 2022

This is a convenience for users who may template their functions/classes on SYCL pipe types.
This allows them to do something like:

template<typename MyPipe>
void foo(/* ... */) {
    using PipeT = MyPipe::value_type;
    // ...
}

Test update: intel/llvm-test-suite#800

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@againull againull left a comment

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I am sorry for the late review.

@tyoungsc tyoungsc requested a review from a team as a code owner February 22, 2022 20:29
@againull againull self-requested a review February 23, 2022 16:28
againull
againull previously approved these changes Feb 23, 2022
@bader bader requested review from MrSidims and againull March 2, 2022 15:20
@bader bader changed the title [SYCL] [FPGA] Exposing value_type and min_capacity from SYCL pipes extension class [SYCL][FPGA] Expose value_type and min_capacity from SYCL pipes extension class Mar 3, 2022
@bader bader merged commit e1619fa into intel:sycl Mar 3, 2022
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6 participants