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[LIBCLC][CUDA] Apply always_inline to all atomics #5710

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Merged
merged 1 commit into from
Mar 3, 2022
Merged

[LIBCLC][CUDA] Apply always_inline to all atomics #5710

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6 changes: 4 additions & 2 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_cmpxchg.cl
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Original file line number Diff line number Diff line change
Expand Up @@ -76,10 +76,12 @@ Memory order is stored in the lowest 5 bits */

#define __CLC_NVVM_ATOMIC_CAS(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
OP, OP_MANGLED) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_CAS_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
OP_MANGLED, __global, AS1, _global_) \
__CLC_NVVM_ATOMIC_CAS_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
OP_MANGLED, __local, AS3, _shared_)
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_CAS_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
OP, OP_MANGLED, __local, AS3, _shared_)

__CLC_NVVM_ATOMIC_CAS(int, i, int, i, cas, CompareExchange)
__CLC_NVVM_ATOMIC_CAS(long, l, long, l, cas, CompareExchange)
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6 changes: 4 additions & 2 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_helpers.h
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Expand Up @@ -78,9 +78,11 @@ Memory order is stored in the lowest 5 bits */

#define __CLC_NVVM_ATOMIC(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED, __global, AS1, _global_) \
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED, __local, AS3, _shared_)
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED, __local, AS3, _shared_)

#endif
3 changes: 2 additions & 1 deletion libclc/ptx-nvidiacl/libspirv/atomic/atomic_inc_dec_helpers.h
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Expand Up @@ -27,8 +27,9 @@
}

#define __CLC_NVVM_ATOMIC_INCDEC(TYPE, TYPE_MANGLED, OP_MANGLED, VAL) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_INCDEC_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, VAL, __global, \
AS1) \
AS1) __attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_INCDEC_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, VAL, __local, \
AS3)

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9 changes: 5 additions & 4 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_load.cl
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Expand Up @@ -64,10 +64,11 @@ Memory order is stored in the lowest 5 bits */
}

#define __CLC_NVVM_ATOMIC_LOAD(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV) \
__CLC_NVVM_ATOMIC_LOAD_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
__global, AS1, _global_) \
__CLC_NVVM_ATOMIC_LOAD_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
__local, AS3, _shared_)
__attribute__((always_inline)) __CLC_NVVM_ATOMIC_LOAD_IMPL( \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, __global, AS1, _global_) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_LOAD_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, \
TYPE_MANGLED_NV, __local, AS3, _shared_)

__CLC_NVVM_ATOMIC_LOAD(int, i, int, i)
__CLC_NVVM_ATOMIC_LOAD(uint, j, int, i)
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6 changes: 4 additions & 2 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_max.cl
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Expand Up @@ -70,10 +70,12 @@ __CLC_NVVM_ATOMIC(unsigned long, m, unsigned long, ul, max,

#define __CLC_NVVM_ATOMIC_MAX(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, \
OP_MANGLED) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_MAX_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, \
OP_MANGLED, __global, AS1) \
__CLC_NVVM_ATOMIC_MAX_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, \
OP_MANGLED, __local, AS3)
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_MAX_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, \
TYPE_INT_MANGLED, OP_MANGLED, __local, AS3)

__CLC_NVVM_ATOMIC_MAX(float, f, int, i, FMaxEXT)
__CLC_NVVM_ATOMIC_MAX(double, d, long, l, FMaxEXT)
6 changes: 4 additions & 2 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_min.cl
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Expand Up @@ -68,10 +68,12 @@ __CLC_NVVM_ATOMIC(ulong, m, ulong, ul, min, _Z18__spirv_AtomicUMin)

#define __CLC_NVVM_ATOMIC_MIN(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, \
OP_MANGLED) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_MIN_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, \
OP_MANGLED, __global, AS1) \
__CLC_NVVM_ATOMIC_MIN_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, \
OP_MANGLED, __local, AS3)
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_MIN_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, \
TYPE_INT_MANGLED, OP_MANGLED, __local, AS3)

__CLC_NVVM_ATOMIC_MIN(float, f, int, i, FMinEXT)
__CLC_NVVM_ATOMIC_MIN(double, d, long, l, FMinEXT)
9 changes: 5 additions & 4 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_store.cl
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Expand Up @@ -65,10 +65,11 @@ Memory order is stored in the lowest 5 bits */
}

#define __CLC_NVVM_ATOMIC_STORE(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV) \
__CLC_NVVM_ATOMIC_STORE_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
__global, AS1, _global_) \
__CLC_NVVM_ATOMIC_STORE_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
__local, AS3, _shared_)
__attribute__((always_inline)) __CLC_NVVM_ATOMIC_STORE_IMPL( \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, __global, AS1, _global_) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_STORE_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, \
TYPE_MANGLED_NV, __local, AS3, _shared_)

__CLC_NVVM_ATOMIC_STORE(int, i, int, i)
__CLC_NVVM_ATOMIC_STORE(uint, j, int, i)
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4 changes: 3 additions & 1 deletion libclc/ptx-nvidiacl/libspirv/atomic/atomic_sub.cl
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Expand Up @@ -24,8 +24,10 @@
}

#define __CLC_NVVM_ATOMIC_SUB(TYPE, TYPE_MANGLED, OP_MANGLED) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_SUB_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, __global, AS1) \
__CLC_NVVM_ATOMIC_SUB_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, __local, AS3)
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_SUB_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, __local, AS3)

__CLC_NVVM_ATOMIC_SUB(int, i, ISub)
__CLC_NVVM_ATOMIC_SUB(unsigned int, j, ISub)
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