Skip to content

[SYCL][ESIMD] Enable SVM gather/scatter for 1, 2 and 4 elements #5780

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Mar 11, 2022
Merged
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
10 changes: 6 additions & 4 deletions sycl/include/sycl/ext/intel/esimd/memory.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -121,7 +121,8 @@ __ESIMD_API SurfaceIndex get_surface_index(AccessorTy acc) {
/// any element's memory location can be disabled via the input vector of
/// predicates (mask).
/// @tparam Tx Element type, must be of size 4 or less.
/// @tparam N Number of elements to read; can be \c 8, \c 16 or \c 32.
/// @tparam N Number of elements to read; can be \c 1, \c 2, \c 4, \c 8, \c 16
/// or \c 32.
/// @param p The base address.
/// @param offsets the vector of 32-bit offsets in bytes. For each lane \c i,
/// ((byte*)p + offsets[i]) must be element size aligned.
Expand All @@ -130,7 +131,7 @@ __ESIMD_API SurfaceIndex get_surface_index(AccessorTy acc) {
/// undefined.
///
template <typename Tx, int N, class T = detail::__raw_t<Tx>>
__ESIMD_API std::enable_if_t<N == 8 || N == 16 || N == 32, simd<Tx, N>>
__ESIMD_API std::enable_if_t<detail::isPowerOf2(N, 32), simd<Tx, N>>
gather(const Tx *p, simd<uint32_t, N> offsets, simd_mask<N> mask = 1) {
simd<uint64_t, N> offsets_i = convert<uint64_t>(offsets);
simd<uint64_t, N> addrs(reinterpret_cast<uint64_t>(p));
Expand All @@ -154,15 +155,16 @@ gather(const Tx *p, simd<uint32_t, N> offsets, simd_mask<N> mask = 1) {
/// value of the corresponding element in the input offset vector. Access to
/// any element's memory location can be disabled via the input mask.
/// @tparam Tx Element type, must be of size 4 or less.
/// @tparam N Number of elements to write; can be \c 8, \c 16 or \c 32.
/// @tparam N Number of elements to write; can be \c 1, \c 2, \c 4, \c 8, \c 16
/// or \c 32.
/// @param p The base address.
/// @param offsets A vector of 32-bit offsets in bytes. For each lane \c i,
/// ((byte*)p + offsets[i]) must be element size aligned.
/// @param vals The vector to scatter.
/// @param mask The access mask, defaults to all 1s.
///
template <typename Tx, int N, class T = detail::__raw_t<Tx>>
__ESIMD_API std::enable_if_t<N == 8 || N == 16 || N == 32>
__ESIMD_API std::enable_if_t<detail::isPowerOf2(N, 32)>
scatter(Tx *p, simd<uint32_t, N> offsets, simd<Tx, N> vals,
simd_mask<N> mask = 1) {
simd<uint64_t, N> offsets_i = convert<uint64_t>(offsets);
Expand Down