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[SYCL][FPGA] Expose value_type and min_capacity from sycl::ext::intel::experimental::pipe #5896

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[SYCL][FPGA] Expose value_type and min_capacity from sycl::ext::intel::experimental::pipe #5896

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4 changes: 4 additions & 0 deletions sycl/doc/extensions/supported/sycl_ext_intel_dataflow_pipes.asciidoc
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Original file line number Diff line number Diff line change
Expand Up @@ -691,6 +691,10 @@ class pipe {
static dataT read( bool &success_code );
template <class... _Params>
static void write( const dataT &data, bool &success_code );

// Static members
using value_type = dataT;
size_t min_capacity = min_capacity;
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Suggested change
size_t min_capacity = min_capacity;
static constexpr size_t min_capacity = min_capacity;

}
} // namespace sycl::ext::intel::experimental
----
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5 changes: 3 additions & 2 deletions sycl/include/sycl/ext/intel/experimental/pipes.hpp
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Expand Up @@ -21,6 +21,8 @@ namespace experimental {

template <class _name, class _dataT, int32_t _min_capacity = 0> class pipe {
public:
using value_type = _dataT;
static constexpr int32_t min_capacity = _min_capacity;
// Non-blocking pipes
// Reading from pipe is lowered to SPIR-V instruction OpReadPipe via SPIR-V
// friendly LLVM IR.
Expand Down Expand Up @@ -159,10 +161,9 @@ template <class _name, class _dataT, int32_t _min_capacity = 0> class pipe {
private:
static constexpr int32_t m_Size = sizeof(_dataT);
static constexpr int32_t m_Alignment = alignof(_dataT);
static constexpr int32_t m_Capacity = _min_capacity;
#ifdef __SYCL_DEVICE_ONLY__
static constexpr struct ConstantPipeStorage m_Storage = {m_Size, m_Alignment,
m_Capacity};
min_capacity};

// FPGA BE will recognize this function and extract its arguments.
// TODO: Pass latency control parameters via the __spirv_* builtin when ready.
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