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[SYCL] Increase max _BitInt size in FPGA to 4096 #6376

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Merged
merged 1 commit into from
Jun 30, 2022
Merged

[SYCL] Increase max _BitInt size in FPGA to 4096 #6376

merged 1 commit into from
Jun 30, 2022

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premanandrao
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The FPGA backend is able to support a max _BitInt size of 4096. This change raises it
from the previous max of 2048 and adjusts tests accordingly.

@premanandrao
[SYCL] Increase max _Bitint size in fpgs to 4096
d42a150 
The FPGA backend is able to support (and needs) a max _Bitint size
of 4096.  This change raises it from the previous max of 2048 and
adjusts tests accordingly.
@premanandrao premanandrao requested a review from a team as a code owner June 30, 2022 08:30
@pvchupin pvchupin merged commit 3f06cad into intel:sycl Jun 30, 2022
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@erichkeane erichkeane erichkeane approved these changes

@elizabethandrews elizabethandrews elizabethandrews approved these changes

@smanna12 smanna12 smanna12 approved these changes

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@premanandrao @erichkeane @elizabethandrews @smanna12 @pvchupin