[SPIR-V][DOC] Add SPV_INTEL_tensor_float32_rounding extension

sycl/doc/design/spirv-extensions/SPV_INTEL_tensor_float32_rounding.asciidoc

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+:extension_name: SPV_INTEL_tensor_float32_rounding
+:capability_tf32_rounding_name: TensorFloat32RoundingINTEL
+:capability_tf32_rounding_token: 6425
+:RoundFToTF32_name: OpRoundFToTF32INTEL
+:RoundFToTF32_token: 6426
+
+{extension_name}
+================
+
+== Name Strings
+
+{extension_name}
+
+== Contact
+
+To report problems with this extension, please open a new issue at:
+
+https://github.com/intel/llvm
+
+== Contributors
+
+- Dmitry Sidorov, Intel +
+- Victor Mustya, Intel +
+- Kacper Kasper, Intel +
+- Ben Ashbaugh, Intel +
+
+== Notice
+
+Copyright (c) 2023 Intel Corporation.  All rights reserved.
+
+== Status
+
+Working Draft
+
+This is a preview extension specification, intended to provide early access to a
+feature for review and community feedback. When the feature matures, this
+specification may be released as a formal extension.
+
+
+Because the interfaces defined by this specification are not final and are
+subject to change they are not intended to be used by shipping software
+products. If you are interested in using this feature in your software product,
+please let us know!
+
+== Version
+
+[width="40%",cols="25,25"]
+|========================================
+| Last Modified Date | 2023-02-09
+| Revision           | 2
+|========================================
+
+== Dependencies
+
+This extension is written against the SPIR-V Specification,
+Version 1.6 Revision 2.
+
+This extension requires SPIR-V 1.0.
+
+== Overview
+
+This extension adds rounding instruction from float to tensor float (TF32)
+data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits for a
+fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
+instruction below uses 32-bit float type to represent TF32 value.
+
+
+== Extension Name
+
+
+To use this extension within a SPIR-V module, the appropriate *OpExtension* must
+be present in the module:
+
+[subs="attributes"]
+----
+OpExtension "{extension_name}"
+----
+
+== New Capabilities
+
+This extension introduces new capabilities:
+
+[subs="attributes"]
+----
+{capability_tf32_rounding_name}
+----
+
+== New Instructions
+
+Instructions added under the *{capability_tf32_rounding_name}* capability:
+
+[subs="attributes"]
+----
+{RoundFToTF32_name}
+----
+
+
+== Token Number Assignments
+
+[width="40%"]
+[cols="70%,30%"]
+[grid="rows"]
+|====
+|*{capability_tf32_rounding_name}* | {capability_tf32_rounding_token}
+|{RoundFToTF32_name} | {RoundFToTF32_token}
+|====
+
+== Modifications to the SPIR-V Specification, Version 1.6
+
+=== Capabilities
+
+Modify Section 3.31, Capability, adding rows to the Capability table:
+
+--
+[options="header"]
+|====
+2+^| Capability ^| Implicitly Declares 
+| {capability_tf32_rounding_token} | *{capability_tf32_rounding_name}*
+| Enables a rounding instruction from float to tf32 data format +
+ +
+See also extension: *{extension_name}*
+|====
+--
+
+
+=== Instructions
+
+==== 3.42.11. Conversion Instructions
+
+[cols="1,1,3*3",width="100%"]
+|=====
+4+|[[OpRoundFToTF32]]*{RoundFToTF32_name}* +
+ +
+Convert value numerically from a 32-bit floating point type to *TF32*.
+It rounds up 13th bit of a float value and zero out last 13 bits. +
+ +
+'Result Type' must be a scalar or vector of 32-bit floating-point type. +
+ +
+'Float Value' must have the same type as 'Result Type'. +
+ +
+If 'Float Value' is an infinity, the result is the same infinity. If 'Float Value'
+is a NaN, the result is a NaN, but not necessarily the same NaN. +
+ +
+The *RelaxedPrecision* <<Decoration,Decoration>> has no effect on this instruction. +
+ +
+Results are computed per component. +
+ +
+1+|Capability: +
+*{capability_tf32_rounding_name}*
+1+| 4 | {RoundFToTF32_token}
+| '<id>' +
+'Result Type'
+| 'Result <id>'
+| '<id>' +
+'Float Value'
+| '<id>' +
+|=====
+
+
+== Issues
+
+// . first issue
+// +
+// --
+// *RESOLVED*:
+// --
+
+== Revision History
+
+[cols="5,15,15,70"]
+[grid="rows"]
+[options="header"]
+|========================================
+|Rev|Date|Author|Changes
+|1|2022-08-22|Dmitry Sidorov|Initial revision
+|2|2023-02-09|Dmitry Sidorov| Rename the instruction and the extension
+|========================================