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Oct 31, 2022
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596fdf7
llvm-reduce: Add volatile reduction pass
arsenm Oct 21, 2022
b1e1719
llvm-reduce: Add atomic syncscope reduction
arsenm Oct 21, 2022
83da1a6
llvm-reduce: Add a reduction to replace atomics with non-atomics
arsenm Oct 21, 2022
f45ef23
llvm-reduce: Fix some broken test checks
arsenm Oct 23, 2022
827f01c
llvm-reduce: Remove okToRemove logic in block reduction
arsenm Oct 18, 2022
597b9b7
CodeExtractor: Fix assertion with non-0 alloca address spaces
arsenm Oct 19, 2022
cfd0769
[gn build] Port 27902eea0f0a
llvmgnsyncbot Oct 23, 2022
bb1c8b1
[gn build] Port 596fdf75d99f
llvmgnsyncbot Oct 23, 2022
718a979
[M68k][NFC] Use OS and ABI agnostic triple in codegen tests
mshockwave Oct 23, 2022
3e6f7ab
llvm-reduce: Fix opcode reduction leaving behind dead instructions
arsenm Oct 22, 2022
08d1c43
llvm-reduce: Add conditional reduction passes
arsenm Oct 13, 2022
2bb50a5
[clang] Fix time profile in "isIntegerConstantExpr"
Izaron Oct 23, 2022
c64d281
[flang] Add atomic_define and atomic_ref to list of intrinsics
ktras Sep 20, 2022
51b93d5
Merge from 'main' to 'sycl-web' (182 commits)
haonanya1 Oct 24, 2022
9cedab6
[NFC][M68k] Update the status of ISA implementation
0x59616e Oct 24, 2022
f3713a9
[mlir] Support overriding LLVM_LIT_ARGS in standalone builds
mgorny Oct 23, 2022
2c155d3
[llvm-debuginfo-analyzer] (06/09) - Warning and internal options
CarlosAlbertoEnciso Oct 21, 2022
ae34f96
[gn build] Port 2c155d379960
llvmgnsyncbot Oct 24, 2022
fb937c4
[NFC][X86] Fix typo: stric => strict
0x59616e Oct 24, 2022
1d4fd09
[llvm-debuginfo-analyzer] (06/09) - Warning and internal options
CarlosAlbertoEnciso Oct 24, 2022
81ad624
[llvm-debuginfo-analyzer] Fix shared build. NFC.
darkbuck Oct 24, 2022
6cee539
[Clang] Change AnonStructIds in MangleContext to per-function based
xur-llvm Oct 24, 2022
0dce4cc
[mlir] Fix a warning
kazutakahirata Oct 24, 2022
eccdedd
[AMDGPU] Autogenerate icmp codegen test
Pierre-vh Oct 21, 2022
edb68a4
[LIT] Add AArch64/Windows to LP64 feature
omjavaid Oct 17, 2022
38389f3
[lldb][Test] Add CPlusPlusNameParser unit-test: C-array function argu…
Michael137 Oct 24, 2022
82c6f10
[mlir] Better handling for bit groups in enum parser/printer
River707 Oct 22, 2022
c8496d2
[mlir] Refactor alias generation to support nested aliases
River707 Oct 22, 2022
3bef1e0
[mlir:LLVM] Add attribute/op definitions for debug info
River707 Oct 22, 2022
88f4cdd
[mlir][Bazel] Port 3bef1e0f4c1d7fd901b58abe0c5c0e67da764ba2
akuegel Oct 24, 2022
3be0593
[LoongArch] Add support for ISD::FRAMEADDR and ISD::RETURNADDR
gonglingqin Oct 24, 2022
c6fa574
[ADT] Remove redundant typename (NFC)
kazutakahirata Oct 24, 2022
a1317be
[SelectionDAG] Use std::clamp (NFC)
kazutakahirata Oct 24, 2022
b169643
[mlir][interfaces] Remove getDestinationOperands from TilingInterface
matthias-springer Oct 24, 2022
e98a4c5
[llvm-debuginfo-analyzer] (07/09) - Compare elements
CarlosAlbertoEnciso Oct 24, 2022
b503923
[gn build] Port e98a4c5acb37
llvmgnsyncbot Oct 24, 2022
f8b8426
[RISCV] Add Svnapot extension
BeMg Oct 24, 2022
6909014
[libc] mem* framework v3
gchatelet Oct 22, 2022
fd5f3ab
[DAG] Fold (abs (sign_extend_inreg x)) -> (zero_extend (abs (truncate…
RKSimon Oct 24, 2022
97bd44f
[llvm-exegesis] getNonRedundantWriteProcRes - perform basic toplogica…
RKSimon Oct 24, 2022
55509b1
[libc] Fix broken tests on arm32
gchatelet Oct 24, 2022
282fe50
[libc] Fix generic 32-bit implementation of Bcmp/Memcmp
gchatelet Oct 24, 2022
8d06ef5
[LLDB] Check that RegisterInfo and ContextInfo are trivial
DavidSpickett Oct 24, 2022
d152393
[lldb] Add LLVM include dirs prior to gtest target in standalone build
mgorny Oct 23, 2022
6f1e430
[AArch64] Alter v8.5a FRINT neon intrinsics to be target-based, not p…
davemgreen Oct 24, 2022
d7917fd
[libc] Use cpp::byte instead of char in mem* functions
gchatelet Oct 24, 2022
0e0c82b
[libc] Fix BUILD.bazel missing dependency
gchatelet Oct 24, 2022
12c9cb6
[llvm-exegesis] Fix missing dependency in BUILD.bazel
gchatelet Oct 24, 2022
fc28971
Add nocapture to pointer parameters of masked stores/loads
MacDue Oct 24, 2022
8d995c0
[gn build] port 97bd44f436ea
nico Oct 24, 2022
51b98db
GlobalISel: Precommit for artifact combine patches
petar-avramovic Oct 24, 2022
f1aa598
GlobalISel: Artifact combine merge-like and unmerge into copy
petar-avramovic Oct 24, 2022
e6c778f
GlobalISel: Artifact combine merge-like and unmerge into unmerge
petar-avramovic Oct 24, 2022
cbc378e
GlobalISel: Artifact combine merge-like and unmerges into merge-like
petar-avramovic Oct 24, 2022
9ec7448
[Clang][AArch64] Add support for -mcpu=grace
sjoerdmeijer Oct 24, 2022
c9b3638
[mlir][scf][bufferize] Fix bufferizesToMemoryRead with 0 loop iterations
matthias-springer Oct 24, 2022
1534b04
Fix caret position to be on the non null parameter
Grillo-0 Oct 24, 2022
41c42f5
[InstCombine] adjust mul tests to avoid reliance on other folds; NFC
rotateright Oct 24, 2022
56c6b61
[InstCombine] vary commuted patterns for mul fold; NFC
rotateright Oct 24, 2022
d84e4f0
[mlir] Apply ClangTidy performance fix (NFC)
akuegel Oct 24, 2022
b7c9226
GH58368: Correct concept checking in a lambda defined in concept
Oct 20, 2022
c14ef2d
[flang] Add kernel to lower expressions to HLFIR
jeanPerier Oct 24, 2022
e28e214
[X86] Treat PSLLDQ/PSRLDQ as a shuffle not a shift
RKSimon Oct 24, 2022
52f3985
[lldb] Include gtest in standalone build only if LLDB_INCLUDE_TESTS
mgorny Oct 23, 2022
72711d4
[AMDGPU][MC] Correct definition of aliases
dpreobra Oct 24, 2022
65aaecc
Revert "[TargetLowering][RISCV][X86] Support even divisors in expandD…
topperc Oct 24, 2022
7153010
[PowerPC] Fix invalid cast for vector shuffles when lowering to the x…
amy-kwan Oct 22, 2022
bddd9b6
[InstCombine] Combine ptrauth sign/resign + auth/resign intrinsics.
ahmedbougacha Oct 24, 2022
ce286ec
[IncludeCleaner] Add public API
kadircet Oct 19, 2022
5b70001
[AArch64][PAC] Add helper enum/functions to handle PAC keys/ops.
ahmedbougacha Oct 24, 2022
718bb22
[AArch64][PAC] Select XPAC for ptrauth.strip intrinsic.
ahmedbougacha Oct 24, 2022
cfb88ee
[StrictFP][IPSCCP] Constant fold intrinsics with metadata arguments
kpneal Oct 24, 2022
d0d2772
[Clang] Implement P2513
cor3ntin Oct 21, 2022
d595378
[flang] Fix building against LLVM dylib
mgorny Oct 24, 2022
73200d1
[lldb-tests] Remove libstdc++ requirement from test
felipepiovezan Oct 24, 2022
c413df0
[lldb-tests] Force use of system stdlib for Objective-C test
felipepiovezan Oct 24, 2022
bca2b14
[mlir][sparse] fix bufferizableOpInterface for InsertOp
Oct 21, 2022
d81919d
[X86] 2012-01-12-extract-sv.ll - add AVX2 test coverage
RKSimon Oct 24, 2022
da4baa9
Fix MSVC "not all control paths return a value" warning. NFC.
RKSimon Oct 24, 2022
1fa8fd4
Recommit "[TargetLowering][RISCV][X86] Support even divisors in expan…
topperc Oct 24, 2022
81713e8
[InstCombine] Fold series of instructions into mull
vfdff Oct 24, 2022
b9e63ab
[lit][REQUIRES] Fix REQUIRES on an NVPTX test so it will run
pogo59 Oct 24, 2022
da4e0f7
[SLP][NFC]Fix PR58476: Fix compile time for reductions, NFC.
alexey-bataev Oct 20, 2022
5293016
Revert "GH58368: Correct concept checking in a lambda defined in conc…
Oct 24, 2022
377f27b
[X86] `DAGTypeLegalizer::ModifyToType()`: when widening w/ zeros, ins…
LebedevRI Oct 24, 2022
1c84831
[XCOFF] llvm-readobj support decoding the loader section header field…
diggerlin Oct 24, 2022
f298bfb
[X86] New test case for reassociation of ADD instructions.
weiguozhi Oct 24, 2022
26fcee6
[ELF] Add --no-warnings/-w
MaskRay Oct 24, 2022
94b8469
[mlir][Tensor] Add a helper build method for pad operations with cons…
Oct 24, 2022
5b17eb1
[lldb] Fix stale diagnostic event comments (NFC)
JDevlieghere Oct 24, 2022
cddea67
[llvm-debuginfo-analyzer] (07/09) - Compare elements
CarlosAlbertoEnciso Oct 24, 2022
1228109
[mlir] Fix INSTALL_INTERFACE path for MLIRSparseTensorEnums
mgorny Oct 24, 2022
551c7ae
[libc] add performance options for string to float
michaelrj-google Oct 21, 2022
093b401
[ARM] Add a test demonstrating reductions with reused extend. NFC
davemgreen Oct 24, 2022
d30727f
[mlir][Translation] Make commandline option registration optional
rkayaith Oct 23, 2022
7e8af2f
[ARM] Support -mexecute-only with -mlong-calls.
zyma98 Oct 24, 2022
016fbc4
[flang] Carry dynamic type in fir.rebox code generation
clementval Oct 24, 2022
b876f6e
Reapply "GH58368: Correct concept checking in a lambda defined in con…
Oct 24, 2022
5f5e019
[mlir][sparse] add some APIs for merger to query the tensor id for ou…
Oct 24, 2022
0487728
[PGO] Make emitted symbols hidden
abrachet Oct 24, 2022
6eaad74
Correct a typo in the release notes; NFC
AaronBallman Oct 24, 2022
f43ef6b
Update the status of more C99 DRs
AaronBallman Oct 24, 2022
7590776
[lldb] Skip TestFullLtoStepping in older clangs
augusto2112 Oct 24, 2022
9c68f8e
[mlir][NVGPU] Documentation only update to nvgpu dialect (NFC).
Oct 19, 2022
5635f00
Fix failing test case
AaronBallman Oct 24, 2022
cecc9a9
Revert "Reapply "GH58368: Correct concept checking in a lambda define…
Oct 24, 2022
440005b
[AArch64]]SME2 multi-vec to multi-vec FP/INT down convert 2/4 registers
CarolineConcatto Oct 10, 2022
11b8795
[clang-format][NFC] Fix comment grammer in ContinuationIndenter
HazardyKnusperkeks Oct 10, 2022
c5755f4
[clang-format] Handle unions like structs and classes
HazardyKnusperkeks Oct 11, 2022
006bf8d
[clang-format][NFC] Handle language specific stuff at the top...
HazardyKnusperkeks Oct 10, 2022
1edc51b
[InstCombine] Explicitly check for scalable TypeSize.
topperc Oct 24, 2022
e3bb359
[clang][Toolchains][Gnu] pass -g through to assembler
nickdesaulniers Oct 24, 2022
18066b5
[mlir] Update Location to use new casting infra
nkreeger Oct 24, 2022
975740b
"Reapply "GH58368: Correct concept checking in a lambda defined in co…
Oct 24, 2022
c3ead85
[RISCV][clang] Support RISC-V vectors in UninitializedValues.
topperc Oct 24, 2022
3637dc6
[clang][CodeGen] Consistently return nullptr Values for void builtins…
zero9178 Oct 24, 2022
bd7949b
reland e5581df60a35 [SimplifyCFG] accumulate bonus insts cost
yxsamliu Sep 17, 2022
c782a93
[Instcombine] Add coverage for demanded bits of insertelement
preames Oct 24, 2022
0de10a6
Fix a failing C DR test case found by post-commit CI
AaronBallman Oct 24, 2022
5dcfc32
[InstCombine] allow more commutative matches for logical-and to selec…
rotateright Oct 24, 2022
6613f4a
[ORC] Use raw OS handle values, ExecutorAddr for EPC dylib handles.
lhames Oct 24, 2022
c977251
[ORC] Allow EPCEHFrameRegistrar clients to specify registration funct…
lhames Oct 24, 2022
0c35b61
[ASAN] Don't inline when -asan-max-inline-poisoning-size=0
Oct 18, 2022
996267d
[DirectX backend] set target triple to "dxil-ms-dx"
python3kgae Oct 24, 2022
1220442
[libc] Add implementation of difftime function.
rtenneti-google Oct 24, 2022
1acffe8
NFC: [clang] Template argument cleanups.
mizvekov Oct 24, 2022
cec276a
[libc] Build fix.
rtenneti-google Oct 24, 2022
dd00c4d
Fix breakpoint setting so it always works when there is a line entry …
clayborg Oct 18, 2022
67ad31c
[MSAN] Count Zeroes test for covering ctlz and cttz under MSAN. (NFC)
kda Oct 22, 2022
6faf40b
[libc] Add the header sys/types.h.
Oct 24, 2022
31bfa4a
[MSAN] Add handleCountZeroes for ctlz and cttz.
kda Oct 25, 2022
d39486d
[ASAN] Remove asserts introduced in https://reviews.llvm.org/D136197
Oct 24, 2022
dc17043
[clang] Fix missing diagnostic of declaration use when accessing Type…
mizvekov Oct 22, 2022
0c849ad
[Polly][docs] Avoid use of code-block:: guess.
Meinersbur Oct 24, 2022
1d31ea6
Fix LazyInitialization in tsan
ZijunZhaoCCK Oct 25, 2022
345b058
[memprof] Respect COMPILER_RT_BUILD_MEMPROF when install memprof headers
Enna1 Oct 25, 2022
686a951
[flang] Make default quad precision kind target dependent
PeixinQiao Oct 25, 2022
ac44cb7
[flang] Add two semantic checks about BIND(C) attribute
PeixinQiao Oct 25, 2022
37e754e
[clang-format] Insert closing braces after an unaffected line
owenca Oct 23, 2022
63ed3d0
[RISCV] Rename lowerFTRUNC_FCEIL_FFLOOR_FROUND to lowerVectorFTRUNC_F…
topperc Oct 25, 2022
d4dc036
[RISCV] Move vector cost table lookup out of the switch in getIntrins…
topperc Oct 25, 2022
223f466
[RISCV] Add ORI to hasAllNBitUsers.
topperc Oct 25, 2022
49e2d36
Add a document on side effects & speculation in MLIR
Oct 13, 2022
a54f334
[RISCV] Add shift amount operands of shift, rotate, and Zbs instructi…
topperc Oct 25, 2022
b0fc18d
[ompd] Fix gdb-plugin warnings after D100185
MaskRay Oct 25, 2022
9af92ed
[mlir:LLVM] Rewrite the LLVMIR export to use the debug info attributes
River707 Oct 22, 2022
11ed12f
llvm-reduce: Remove pointless template arguments
arsenm Oct 24, 2022
df60f0b
llvm-reduce: Remove unnecessary arguments from test
arsenm Oct 24, 2022
6951cec
[flang] Allow all OSes in fir::CodeGenSpecifics::get
MaskRay Oct 25, 2022
fdac4c4
[X86] Add CMPCCXADD instructions.
FreddyLeaf Oct 25, 2022
a704782
[gn build] Port fdac4c4e92e5
llvmgnsyncbot Oct 25, 2022
e6c8418
[ObjCARC][NFC] Fix defined but not used warning from D135041
ChunyuLiao Oct 25, 2022
3a3603f
[clang] Replace BACKEND_PACKAGE_STRING with LLVM_VERSION_STRING
MaskRay Oct 25, 2022
772fc63
[IncludeCleaner] Handle more C++ constructs
kadircet Aug 17, 2022
fd1d93d
[clang-format] Mark pragma region lines as StringLiterals
tru Oct 25, 2022
9c48b7f
[AArch64][ARM] Alter v8.1a neon intrinsics to be target-based, not pr…
davemgreen Oct 25, 2022
021ed4c
[AArch64]SME2 Single and multiple vectors SVE Destructive two/four re…
CarolineConcatto Oct 21, 2022
885dadf
[NFC] Fix merge mistake in TokenAnnotator.cpp
tru Oct 25, 2022
ecd78ec
[AArch64]SME2 Multiple vectors Int/FP clamp instructions for two/four…
CarolineConcatto Oct 21, 2022
19b9e62
[AArch64][SME] Fix chain for arm_locally_streaming functions.
sdesmalen-arm Oct 25, 2022
325927f
[X86] Update LiveVariables in more cases in convertToThreeAddress
jayfoad Oct 24, 2022
0243057
[MachineVerifier] Try harder to verify LiveVariables
jayfoad Jul 6, 2022
a4e8492
[AArch64]SME2 Multi-vector ternary indexed DOT and FMLA instructions
CarolineConcatto Oct 21, 2022
d6a8a07
[AArch64][SVE2] Add the SVE2.1 bfmlslb and bfmlslt instructions
david-arm Oct 19, 2022
1f23cf4
[NFC][AMDGPU] Pre-commit test for D136432
tsymalla-AMD Oct 25, 2022
5621cae
[AArch64][SVE] NFC: extend tests for flag-setting predicate instructions
c-rhodes Oct 25, 2022
1e02a29
[AArch64][SVE] Use more flag-setting instructions
c-rhodes Oct 25, 2022
d0d9d1e
[clang-format] Move bracket to correct line.
akuegel Oct 25, 2022
e95c74b
[AArch64] Add precommit test for bcmp; NFC
bcl5980 Oct 25, 2022
9bd2730
[Clang][AArch64] Add TargetParser support for defining CPU aliases
sjoerdmeijer Oct 24, 2022
3d9bf8c
[LLDB] Add missing breaks to current frame row in command map
DavidSpickett Oct 25, 2022
1fe096e
[AArch64][SVE2] Add the SVE2.1 signed and unsigned 2-way dot instruct…
david-arm Oct 19, 2022
791fe26
[clang][ExtractAPI] Allow users to specify a list of symbols to ignore
daniel-grumberg Oct 21, 2022
0284148
[libc] Switch to new implementation of mem* functions
gchatelet Oct 24, 2022
05ae747
[LLDB][RISCV] Add RV64C instruction support for EmulateInstructionRISCV
Oct 20, 2022
891eb20
[LLDB][Docs][NFC] Fix formatting in -gmodules documentation
Michael137 Oct 25, 2022
76745d2
Revert "[PGO] Make emitted symbols hidden"
nico Oct 25, 2022
a3be778
[LLDB] [LoongArch] Add minimal LoongArch support
seehearfeel Oct 25, 2022
c4051b2
[X86] Fold vbroadcast(bitcast(vbroadcast(src))) -> bitcast(vbroadcast…
RKSimon Oct 25, 2022
14de3d5
[mlir][llvm] Don't return a dangling reference in getCallableResults().
definelicht Oct 25, 2022
b92725e
[X86] Add test coverage for #58585
RKSimon Oct 25, 2022
af1bb28
[AArch64][ARM] Alter v8.3a complex neon intrinsics to be target-based…
davemgreen Oct 25, 2022
fcbaf6f
[X86] Add v4i64 test coverage for #58585
RKSimon Oct 25, 2022
191d70f
[AMDGPU] Use Register in more places in SIInstrInfo. NFC.
jayfoad Oct 25, 2022
854b1bc
[DebugInfo] getMergedLocation: Maintain the line number if they match
jmmartinez Oct 25, 2022
4ffba0a
[gn build] Port 791fe26d7581
llvmgnsyncbot Oct 25, 2022
89fd81d
[gn build] Port a3be778ed09b
llvmgnsyncbot Oct 25, 2022
3125a4d
[lit][REQUIRES] Fix llvm-debuginfod.test so it will run
pogo59 Oct 24, 2022
ed1b0da
[X86] combineConcatVectorOps - fold v4i64/v8x32 concat(broadcast(),br…
RKSimon Oct 25, 2022
c094b1e
[LLDB] Fix RISCV build
Oct 25, 2022
620cff0
[InstCombine] Fold series of instructions into mull for more types
vfdff Oct 25, 2022
33601f4
[llvm-lit][test] Fix regex to capture scientific notation
gbreynoo Oct 25, 2022
2f88268
[mlir] Add vectorization tests for linalg.map,reduce,transpose.
pifon2a Oct 25, 2022
451b1ff
[mlir] Add lower-to-loops tests for linalg.map/reduce/transpose.
pifon2a Oct 25, 2022
cb088e8
Add more C99 DR test cases and update the status page
AaronBallman Oct 25, 2022
3d0e9ed
[OpenMP] [OMPIRBuilder] Create a new datatype to hold the unique targ…
jsjodin Oct 24, 2022
87ec22d
[mlgo] More wildcarding in extra features logging for regalloc
mtrofin Oct 25, 2022
5be51ac
Speculatively fix the test bots
AaronBallman Oct 25, 2022
9000ee2
[ORC] Update SelfExecutorProcessControl to allow user-supplied handles.
lhames Oct 25, 2022
b3c9ced
[ORC] Allow EPCDebugObjectRegistrar clients to specify registration f…
lhames Oct 25, 2022
9d5adc7
Revert "reland e5581df60a35 [SimplifyCFG] accumulate bonus insts cost"
yxsamliu Oct 25, 2022
60809cd
Revert "[clang] Fix missing diagnostic of declaration use when access…
nico Oct 25, 2022
50fe87a
[Transforms] classifyArgUse - don't deference pointer before null test
RKSimon Oct 25, 2022
6d85926
[lit] Define keyword used by MCJIT test
pogo59 Oct 25, 2022
6fcaaf8
Whitespace fix in a comment; NFC
AaronBallman Oct 25, 2022
93a5a03
[lldb] Host::ShellExpandArguments - fix error check for valid dictionary
RKSimon Oct 25, 2022
0057756
[Clang][NFC] Fix UnicodeData.txt parsing.
cor3ntin Oct 25, 2022
b179351
[SDAG] refactor folds for scalar-to-vector; NFCI
rotateright Oct 25, 2022
96482ee
[SystemZInstPrinter] Introduce markup tags emission
uweigand Oct 25, 2022
3e067d4
[include-cleaner] Move vocabulary types into separate header for laye…
sam-mccall Oct 25, 2022
01b8140
[AMDGPU] Fix delay alu for VOPD with src2acc
Sisyph Oct 20, 2022
dce5bb9
[clang-format] Correctly annotate UDLs as OverloadedOperator
rymiel Sep 29, 2022
d03ee70
[Tooling] Avoid StandardLibrary.h including Decl. NFC
sam-mccall Oct 25, 2022
c34de60
Revert "[mlir] Add vectorization tests for linalg.map,reduce,transpose."
pifon2a Oct 25, 2022
c49d14a
[trace][intel pt] Simple detection of infinite decoding loops
Oct 23, 2022
8c42b5e
[SelectionDAG] Add missing semicolon after return.
topperc Oct 25, 2022
070f414
[AArch64]SME2 single-multi and multi-multi INT/FP dot product instruc…
CarolineConcatto Oct 22, 2022
f770b1e
[flang] Add check for constraints on synchronization-stmts
ktras Oct 17, 2022
9fbd57f
[AArch64]SME2 single-multi and multi-multi INT dot product instructi…
CarolineConcatto Oct 22, 2022
a527bda
[LegacyPM] Remove DataFlowSanitizerLegacyPass
MaskRay Oct 25, 2022
1232f97
[docs] Update clang-formatted-files.txt after bindings/go removal (D1…
MaskRay Oct 25, 2022
20204db
[BOLT] Add mold-style PLT support
maksfb Oct 25, 2022
22ea0e5
[libc] Add Linux implementations of time and clock functions.
Oct 25, 2022
fd5a2bf
[libc++] Add missing includes to xlocale helpers
ldionne Oct 24, 2022
0e8a414
[CUDA, NVPTX] Added basic __bf16 support for NVPTX.
Artem-B Oct 20, 2022
8b0a2f7
Merge from 'sycl' to 'sycl-web'
Oct 25, 2022
f802317
Merge from 'main' to 'sycl-web' (376 commits)
preethi-intel Oct 25, 2022
593676e
Merge remote-tracking branch 'otcshare_llvm/sycl-web' into llvmspirv_…
preethi-intel Oct 26, 2022
4b1c5e1
Integer dot product 4x8 packed translation
Quetzonarch Sep 29, 2022
e29b538
Address issue #1548 after removal most of constant expressions in LLV…
vmaksimo Oct 12, 2022
e05c574
Correctly identify mangling of varargs in the demangler. (#1642)
jcranmer-intel Oct 14, 2022
c5760a9
Emit OpMemberDecorate for member 0 annotations (#1646)
dwoodwor-intel Oct 14, 2022
73f3224
Add opening parenthesis to call checks (#1659)
svenvh Oct 18, 2022
d2641da
Support multiple UserSemantic decorations (#1628)
MrSidims Oct 18, 2022
f098bc4
Reorder SPIR-V blocks to emit dominators first (#1655)
dwoodwor-intel Oct 20, 2022
4743b91
Check for full SPIR-V IR function names (#1665)
svenvh Oct 21, 2022
ff0439c
Fix translation of annotations in opaque-pointers mode (#1643)
MrSidims Oct 21, 2022
b12054a
Translate llvm.loop.unroll.full metadata (#1664)
MrSidims Oct 24, 2022
800bbea
Hotfix LoopUnroll test (#1672)
MrSidims Oct 24, 2022
dbfe3ea
Remove JointMatrixINTEL W/S (#1658)
MrSidims Oct 24, 2022
123375f
[X86] Move 128/256-bit FP16/BF16 typedef to emmintrin.h or or avxintr…
iclsrc Oct 21, 2022
35a48cb
[NFC] Fix SemaSYCL::unnamed-kernel.cpp test
Fznamznon Oct 17, 2022
2c805fc
[SYCL] Fix integration header on Windows
Fznamznon Oct 21, 2022
e1f57fa
[NFC] Add opaque-pointers option
haonanya1 Oct 25, 2022
ae3dda4
[NFC] Add opaque-pointers options
haonanya1 Oct 18, 2022
43c51e8
Add -opaque-pointers option to the LIT test
preethi-intel Oct 26, 2022
344612e
Fix for build fail in LibclcRemangler.cpp because of undeclared ident…
nawalcopty Oct 25, 2022
8775645
(1) Fix for test using new offloading path. Patch by Toguchi, Michael…
preethi-intel Oct 29, 2022
ec4d3cf
[X86] Move of 128/256-bit FP16/BF16 typedef to emmintrin.h or avxintr…
preethi-intel Oct 30, 2022
79509df
Disable __bf16 errors for SPIR targets
preethi-intel Oct 30, 2022
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43 changes: 31 additions & 12 deletions bolt/include/bolt/Core/BinaryContext.h
Original file line number Diff line number Diff line change
Expand Up @@ -179,6 +179,10 @@ class BinaryContext {
using NameToSectionMapType = std::multimap<std::string, BinarySection *>;
NameToSectionMapType NameToSection;

/// Map section references to BinarySection for matching sections in the
/// input file to internal section representation.
DenseMap<SectionRef, BinarySection *> SectionRefToBinarySection;

/// Low level section registration.
BinarySection &registerSection(BinarySection *Section);

Expand Down Expand Up @@ -224,6 +228,9 @@ class BinaryContext {
/// DWARF line info for CUs.
std::map<unsigned, DwarfLineTable> DwarfLineTablesCUMap;

/// Internal helper for removing section name from a lookup table.
void deregisterSectionName(const BinarySection &Section);

public:
static Expected<std::unique_ptr<BinaryContext>>
createBinaryContext(const ObjectFile *File, bool IsPIC,
Expand Down Expand Up @@ -951,13 +958,13 @@ class BinaryContext {
BinarySection &registerSection(SectionRef Section);

/// Register a copy of /p OriginalSection under a different name.
BinarySection &registerSection(StringRef SectionName,
BinarySection &registerSection(const Twine &SectionName,
const BinarySection &OriginalSection);

/// Register or update the information for the section with the given
/// /p Name. If the section already exists, the information in the
/// section will be updated with the new data.
BinarySection &registerOrUpdateSection(StringRef Name, unsigned ELFType,
BinarySection &registerOrUpdateSection(const Twine &Name, unsigned ELFType,
unsigned ELFFlags,
uint8_t *Data = nullptr,
uint64_t Size = 0,
Expand All @@ -967,7 +974,7 @@ class BinaryContext {
/// with the given /p Name. If the section already exists, the
/// information in the section will be updated with the new data.
BinarySection &
registerOrUpdateNoteSection(StringRef Name, uint8_t *Data = nullptr,
registerOrUpdateNoteSection(const Twine &Name, uint8_t *Data = nullptr,
uint64_t Size = 0, unsigned Alignment = 1,
bool IsReadOnly = true,
unsigned ELFType = ELF::SHT_PROGBITS) {
Expand All @@ -976,10 +983,16 @@ class BinaryContext {
Size, Alignment);
}

/// Remove sections that were preregistered but never used.
void deregisterUnusedSections();

/// Remove the given /p Section from the set of all sections. Return
/// true if the section was removed (and deleted), otherwise false.
bool deregisterSection(BinarySection &Section);

/// Re-register \p Section under the \p NewName.
void renameSection(BinarySection &Section, const Twine &NewName);

/// Iterate over all registered sections.
iterator_range<FilteredSectionIterator> sections() {
auto notNull = [](const SectionIterator &Itr) { return (bool)*Itr; };
Expand Down Expand Up @@ -1073,20 +1086,26 @@ class BinaryContext {
return const_cast<BinaryContext *>(this)->getSectionForAddress(Address);
}

/// Return internal section representation for a section in a file.
BinarySection *getSectionForSectionRef(SectionRef Section) const {
return SectionRefToBinarySection.lookup(Section);
}

/// Return section(s) associated with given \p Name.
iterator_range<NameToSectionMapType::iterator>
getSectionByName(StringRef Name) {
return make_range(NameToSection.equal_range(std::string(Name)));
getSectionByName(const Twine &Name) {
return make_range(NameToSection.equal_range(Name.str()));
}
iterator_range<NameToSectionMapType::const_iterator>
getSectionByName(StringRef Name) const {
return make_range(NameToSection.equal_range(std::string(Name)));
getSectionByName(const Twine &Name) const {
return make_range(NameToSection.equal_range(Name.str()));
}

/// Return the unique section associated with given \p Name.
/// If there is more than one section with the same name, return an error
/// object.
ErrorOr<BinarySection &> getUniqueSectionByName(StringRef SectionName) const {
ErrorOr<BinarySection &>
getUniqueSectionByName(const Twine &SectionName) const {
auto Sections = getSectionByName(SectionName);
if (Sections.begin() != Sections.end() &&
std::next(Sections.begin()) == Sections.end())
Expand Down Expand Up @@ -1217,10 +1236,10 @@ class BinaryContext {
return Size;
}

/// Verify that assembling instruction \p Inst results in the same sequence of
/// bytes as \p Encoding.
bool validateEncoding(const MCInst &Instruction,
ArrayRef<uint8_t> Encoding) const;
/// Validate that disassembling the \p Sequence of bytes into an instruction
/// and assembling the instruction again, results in a byte sequence identical
/// to the original one.
bool validateInstructionEncoding(ArrayRef<uint8_t> Sequence) const;

/// Return a function execution count threshold for determining whether
/// the function is 'hot'. Consider it hot if count is above the average exec
Expand Down
78 changes: 58 additions & 20 deletions bolt/include/bolt/Core/BinarySection.h
Original file line number Diff line number Diff line change
Expand Up @@ -43,9 +43,12 @@ class BinaryData;
class BinarySection {
friend class BinaryContext;

/// Count the number of sections created.
static uint64_t Count;

BinaryContext &BC; // Owning BinaryContext
std::string Name; // Section name
const SectionRef Section; // SectionRef (may be null)
const SectionRef Section; // SectionRef for input binary sections.
StringRef Contents; // Input section contents
const uint64_t Address; // Address of section in input binary (may be 0)
const uint64_t Size; // Input section size
Expand Down Expand Up @@ -86,6 +89,7 @@ class BinarySection {
uint64_t OutputSize{0}; // Section size in the rewritten binary.
uint64_t OutputFileOffset{0}; // File offset in the rewritten binary file.
StringRef OutputContents; // Rewritten section contents.
const uint64_t SectionNumber; // Order in which the section was created.
unsigned SectionID{-1u}; // Unique ID used for address mapping.
// Set by ExecutableFileMemoryManager.
uint32_t Index{0}; // Section index in the output file.
Expand Down Expand Up @@ -140,20 +144,21 @@ class BinarySection {

public:
/// Copy a section.
explicit BinarySection(BinaryContext &BC, StringRef Name,
explicit BinarySection(BinaryContext &BC, const Twine &Name,
const BinarySection &Section)
: BC(BC), Name(Name), Section(Section.getSectionRef()),
: BC(BC), Name(Name.str()), Section(SectionRef()),
Contents(Section.getContents()), Address(Section.getAddress()),
Size(Section.getSize()), Alignment(Section.getAlignment()),
ELFType(Section.getELFType()), ELFFlags(Section.getELFFlags()),
Relocations(Section.Relocations),
PendingRelocations(Section.PendingRelocations), OutputName(Name) {}
PendingRelocations(Section.PendingRelocations), OutputName(Name.str()),
SectionNumber(++Count) {}

BinarySection(BinaryContext &BC, SectionRef Section)
: BC(BC), Name(getName(Section)), Section(Section),
Contents(getContents(Section)), Address(Section.getAddress()),
Size(Section.getSize()), Alignment(Section.getAlignment()),
OutputName(Name) {
OutputName(Name), SectionNumber(++Count) {
if (isELF()) {
ELFType = ELFSectionRef(Section).getType();
ELFFlags = ELFSectionRef(Section).getFlags();
Expand All @@ -167,13 +172,14 @@ class BinarySection {
}

// TODO: pass Data as StringRef/ArrayRef? use StringRef::copy method.
BinarySection(BinaryContext &BC, StringRef Name, uint8_t *Data, uint64_t Size,
unsigned Alignment, unsigned ELFType, unsigned ELFFlags)
: BC(BC), Name(Name),
BinarySection(BinaryContext &BC, const Twine &Name, uint8_t *Data,
uint64_t Size, unsigned Alignment, unsigned ELFType,
unsigned ELFFlags)
: BC(BC), Name(Name.str()),
Contents(reinterpret_cast<const char *>(Data), Data ? Size : 0),
Address(0), Size(Size), Alignment(Alignment), ELFType(ELFType),
ELFFlags(ELFFlags), IsFinalized(true), OutputName(Name),
OutputSize(Size), OutputContents(Contents) {
ELFFlags(ELFFlags), IsFinalized(true), OutputName(Name.str()),
OutputSize(Size), OutputContents(Contents), SectionNumber(++Count) {
assert(Alignment > 0 && "section alignment must be > 0");
}

Expand Down Expand Up @@ -207,10 +213,34 @@ class BinarySection {

// Order sections by their immutable properties.
bool operator<(const BinarySection &Other) const {
return (getAddress() < Other.getAddress() ||
(getAddress() == Other.getAddress() &&
(getSize() < Other.getSize() ||
(getSize() == Other.getSize() && getName() < Other.getName()))));
// Allocatable before non-allocatable.
if (isAllocatable() != Other.isAllocatable())
return isAllocatable() > Other.isAllocatable();

// Input sections take precedence.
if (hasSectionRef() != Other.hasSectionRef())
return hasSectionRef() > Other.hasSectionRef();

// Compare allocatable input sections by their address.
if (hasSectionRef() && getAddress() != Other.getAddress())
return getAddress() < Other.getAddress();
if (hasSectionRef() && getAddress() && getSize() != Other.getSize())
return getSize() < Other.getSize();

// Code before data.
if (isText() != Other.isText())
return isText() > Other.isText();

// Read-only before writable.
if (isReadOnly() != Other.isReadOnly())
return isReadOnly() > Other.isReadOnly();

// BSS at the end.
if (isBSS() != Other.isBSS())
return isBSS() < Other.isBSS();

// Otherwise, preserve the order of creation.
return SectionNumber < Other.SectionNumber;
}

///
Expand All @@ -228,13 +258,13 @@ class BinarySection {
bool isText() const {
if (isELF())
return (ELFFlags & ELF::SHF_EXECINSTR);
return getSectionRef().isText();
return hasSectionRef() && getSectionRef().isText();
}
bool isData() const {
if (isELF())
return (ELFType == ELF::SHT_PROGBITS &&
(ELFFlags & (ELF::SHF_ALLOC | ELF::SHF_WRITE)));
return getSectionRef().isData();
return hasSectionRef() && getSectionRef().isData();
}
bool isBSS() const {
return (ELFType == ELF::SHT_NOBITS &&
Expand Down Expand Up @@ -406,6 +436,7 @@ class BinarySection {
return SectionID;
}
bool hasValidSectionID() const { return SectionID != -1u; }
bool hasValidIndex() { return Index != 0; }
uint32_t getIndex() const { return Index; }

// mutation
Expand All @@ -416,12 +447,12 @@ class BinarySection {
SectionID = ID;
}
void setIndex(uint32_t I) { Index = I; }
void setOutputName(StringRef Name) { OutputName = std::string(Name); }
void setOutputName(const Twine &Name) { OutputName = Name.str(); }
void setAnonymous(bool Flag) { IsAnonymous = Flag; }

/// Emit the section as data, possibly with relocations. Use name \p NewName
// for the section during emission if non-empty.
void emitAsData(MCStreamer &Streamer, StringRef NewName = StringRef()) const;
/// Emit the section as data, possibly with relocations.
/// Use name \p SectionName for the section during the emission.
void emitAsData(MCStreamer &Streamer, const Twine &SectionName) const;

using SymbolResolverFuncTy = llvm::function_ref<uint64_t(const MCSymbol *)>;

Expand All @@ -430,6 +461,13 @@ class BinarySection {
void flushPendingRelocations(raw_pwrite_stream &OS,
SymbolResolverFuncTy Resolver);

/// Change contents of the section.
void updateContents(const uint8_t *Data, size_t NewSize) {
OutputContents = StringRef(reinterpret_cast<const char *>(Data), NewSize);
OutputSize = NewSize;
IsFinalized = true;
}

/// Reorder the contents of this section according to /p Order. If
/// /p Inplace is true, the entire contents of the section is reordered,
/// otherwise the new contents contain only the reordered data.
Expand Down
14 changes: 12 additions & 2 deletions bolt/include/bolt/Core/MCPlusBuilder.h
Original file line number Diff line number Diff line change
Expand Up @@ -1266,8 +1266,18 @@ class MCPlusBuilder {
/// Replace displacement in compound memory operand with given \p Label.
bool replaceMemOperandDisp(MCInst &Inst, const MCSymbol *Label,
MCContext *Ctx) const {
return replaceMemOperandDisp(
Inst, MCOperand::createExpr(MCSymbolRefExpr::create(Label, *Ctx)));
return replaceMemOperandDisp(Inst, Label, 0, Ctx);
}

/// Replace displacement in compound memory operand with given \p Label
/// plus addend.
bool replaceMemOperandDisp(MCInst &Inst, const MCSymbol *Label,
int64_t Addend, MCContext *Ctx) const {
MCInst::iterator MemOpI = getMemOperandDisp(Inst);
if (MemOpI == Inst.end())
return false;
return setOperandToSymbolRef(Inst, MemOpI - Inst.begin(), Label, Addend,
Ctx, 0);
}

/// Returns how many bits we have in this instruction to encode a PC-rel
Expand Down
41 changes: 41 additions & 0 deletions bolt/include/bolt/Passes/ValidateMemRefs.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,41 @@
//===- bolt/Passes/ValidateMemRefs.h ----------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#ifndef BOLT_PASSES_VALIDATEMEMREFS_H
#define BOLT_PASSES_VALIDATEMEMREFS_H

#include "bolt/Passes/BinaryPasses.h"

namespace llvm::bolt {

/// Post processing to check for memory references that cause a symbol
/// in data section to be ambiguous, requiring us to avoid moving that
/// object or disambiguating such references. This is currently
/// limited to fixing false references to the location of jump tables.
///
class ValidateMemRefs : public BinaryFunctionPass {
public:
explicit ValidateMemRefs(const cl::opt<bool> &PrintPass)
: BinaryFunctionPass(PrintPass) {}

const char *getName() const override { return "validate-mem-refs"; }

void runOnFunctions(BinaryContext &BC) override;

private:
bool checkAndFixJTReference(BinaryFunction &BF, MCInst &Inst,
uint32_t OperandNum, const MCSymbol *Sym,
uint64_t Offset);
void runOnFunction(BinaryFunction &BF);

static std::atomic<std::uint64_t> ReplacedReferences;
};

} // namespace llvm::bolt

#endif
10 changes: 10 additions & 0 deletions bolt/include/bolt/Rewrite/ExecutableFileMemoryManager.h
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,12 @@ class ExecutableFileMemoryManager : public RuntimeDyld::MemoryManager {
};
SmallVector<AllocInfo, 8> AllocatedSections;

// All new sections will be identified by the following prefix.
std::string NewSecPrefix;

// Name prefix used for sections from the input.
std::string OrgSecPrefix;

public:
// Our linker's main purpose is to handle a single object file, created
// by RewriteInstance after reading the input binary and reordering it.
Expand Down Expand Up @@ -86,6 +92,10 @@ class ExecutableFileMemoryManager : public RuntimeDyld::MemoryManager {
void registerEHFrames(uint8_t *Addr, uint64_t LoadAddr,
size_t Size) override {}
void deregisterEHFrames() override {}

/// Section name management.
void setNewSecPrefix(StringRef Prefix) { NewSecPrefix = Prefix; }
void setOrgSecPrefix(StringRef Prefix) { OrgSecPrefix = Prefix; }
};

} // namespace bolt
Expand Down
1 change: 1 addition & 0 deletions bolt/include/bolt/Rewrite/MachORewriteInstance.h
Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,7 @@ class MachORewriteInstance {
void processProfileDataPreCFG();
void processProfileData();

static StringRef getNewSecPrefix() { return ".bolt.new"; }
static StringRef getOrgSecPrefix() { return ".bolt.org"; }

void mapInstrumentationSection(StringRef SectionName);
Expand Down
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