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[SYCL] Implement host pipe unique name generation and mapping calls #8009

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Merged
merged 14 commits into from
Feb 7, 2023

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rho180
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@rho180 rho180 commented Jan 13, 2023

Implementation of host pipes outlined in the design document in this PR:

#5850

  1. Generation a unique pipe id for GVs marked with the new "sycl-host-pipe" attribute. Id generation utilizes the same method as used for name generation for device global.
  2. Added a host pipe map to map the addresses of marked GVs with the unique id. This host pipe map is generated by a constructor and method calls added to the header and footer.
  3. Modified the sycl-post-link tool to generate compile time properties metadata for these GVs. This metadata contains the unique id generated for the GV to be consumed by the device backend compiler.

PR for accompanying runtime changes: #7468

@rho180 rho180 requested review from a team as code owners January 13, 2023 19:32
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Could you please add FE tests?

@steffenlarsen steffenlarsen self-requested a review January 16, 2023 09:17
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rho180 commented Jan 16, 2023

Could you please add FE tests?

Yep, I'll do that


__pipeType __pipe;
}];
}
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@elizabethandrews - Now that we have [[__sycl_detail__::sycl_type(...)]], could this be accomplished using it? If so, we may consider doing the same for [[__sycl_detail__::device_global]]

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I think we can use sycl_type here. I have a JIRA to replace device_global to use sycl_type as well. Just haven't gotten around to it.

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@elizabethandrews @steffenlarsen Are there examples or documentation for sycl_type? I took a quick look in the repo and it's not clear to me how I should use it here.

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@rho180 you can see examples of use here - #6674. You just need to add host_pipe to the definition

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@elizabethandrews @steffenlarsen Updated. Though I know it's not best practice, I copied the static function isSyclType() from SemaSYCL.cpp to do the type check in CodeGenModule. Let me know if there's a common place where this can be put and I can make that change as well.

@@ -9644,6 +9644,9 @@ void SYCLPostLink::ConstructJob(Compilation &C, const JobAction &JA,
// Process device-globals.
addArgs(CmdArgs, TCArgs, {"-device-globals"});

// Process host pipes.
addArgs(CmdArgs, TCArgs, {"-host-pipes"});
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We are planning on moving the CompileTimePropertiesPass to be an LLVM pass rather than a sub-feature of sycl-post-link, in which case we won't need this. See #7527. Note also this may affect the sycl-post-link related changes in this PR, but it should be resolvable.

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@steffenlarsen Now that the CompileTimePropertiesPass change was merged, I rebased, moved my host pipe change out of sycl-post-link, and removed the host-pipe arg from the driver.

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I'm wondering, what is the difference between a host pipe and a device global? Can we just use a device global of a particular type to define a host pipe instead?

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rho180 commented Jan 24, 2023

I'm wondering, what is the difference between a host pipe and a device global? Can we just use a device global of a particular type to define a host pipe instead?

Device globals involve creating storage on the device that is accessible by all kernels. Host pipes can be connected to only one kernel, and do not involve creating storage but are linked to specialized hardware. The commonality is simply that they both require a mechanism to translate addresses in host space to some logical name that the backend compiler knows about.

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Sorry for the delay in review. This PR fell off my radar. FE changes look ok to me. Just a minor comment about test

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(sorry for the late review. My notifications weren't quite working.)
FE changes look okay to me.

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FE part LGTM.

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FE changes look OK to me

@rho180 rho180 requested a review from a team as a code owner February 2, 2023 21:13
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@rho180 rho180 requested review from steffenlarsen and removed request for KseniyaTikhomirova February 6, 2023 13:48
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rho180 commented Feb 6, 2023

@KseniyaTikhomirova I didn't mean to remove you from the review list, I'd only hit the "re-request" button for @steffenlarsen. I'm not sure who else needs to review this to enable merging.

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Missing reviews from @intel/dpcpp-clang-driver-reviewers & @intel/dpcpp-tools-reviewers .

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@KseniyaTikhomirova I didn't mean to remove you from the review list, I'd only hit the "re-request" button for @steffenlarsen. I'm not sure who else needs to review this to enable merging.

Hello, do not worry. Steffen approval is enough on behalf of SYCL RT reviewers side😊

@rho180 rho180 requested a review from AlexeySachkov February 6, 2023 18:14
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sycl-post-link part LGTM

@rho180 rho180 temporarily deployed to aws February 6, 2023 21:06 — with GitHub Actions Inactive
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@bader bader merged commit 752e4d3 into intel:sycl Feb 7, 2023
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