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[SYCL] Move device handling to Unified Runtime #8088

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Merged
merged 14 commits into from
Feb 9, 2023

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@smaslov-intel smaslov-intel commented Jan 24, 2023

The changes although being large, are just move of the code with modifications necessary to being able to share it with L0 Plugin.
Signed-off-by: Sergey V Maslov [email protected]

@smaslov-intel smaslov-intel requested review from a team as code owners January 24, 2023 02:10
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@bso-intel , @igchor , @jandres742 : please review

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Couple of comments, but otherwise looks good.

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LGTM

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+1

Comment on lines 23 to 60
// TODO: promote all of the below extensions to the Unified Runtime
// and get rid of these ZER_EXT constants.
const int ZER_EXT_DEVICE_INFO_END = ZER_DEVICE_INFO_FORCE_UINT32;
const int ZER_EXT_DEVICE_INFO_BUILD_ON_SUBDEVICE = ZER_EXT_DEVICE_INFO_END - 1;
const int ZER_EXT_DEVICE_INFO_MAX_WORK_GROUPS_3D = ZER_EXT_DEVICE_INFO_END - 2;
const int ZER_EXT_DEVICE_INFO_ATOMIC_MEMORY_SCOPE_CAPABILITIES =
ZER_EXT_DEVICE_INFO_END - 3;
const int ZER_EXT_DEVICE_INFO_BFLOAT16_MATH_FUNCTIONS =
ZER_EXT_DEVICE_INFO_END - 4;
const int ZER_EXT_DEVICE_PARTITION_BY_CSLICE = ZER_EXT_DEVICE_INFO_END - 5;
const int ZER_EXT_DEVICE_INFO_MAX_MEM_BANDWIDTH = ZER_EXT_DEVICE_INFO_END - 6;
const int ZER_EXT_DEVICE_INFO_GPU_HW_THREADS_PER_EU =
ZER_EXT_DEVICE_INFO_END - 7;
const int ZER_EXT_DEVICE_INFO_GPU_EU_COUNT_PER_SUBSLICE =
ZER_EXT_DEVICE_INFO_END - 8;
const int ZER_EXT_DEVICE_INFO_GPU_SLICES = ZER_EXT_DEVICE_INFO_END - 9;
const int ZER_EXT_DEVICE_INFO_MAX_COMPUTE_QUEUE_INDICES =
ZER_EXT_DEVICE_INFO_END - 10;
const int ZER_EXT_DEVICE_INFO_MEMORY_BUS_WIDTH = ZER_EXT_DEVICE_INFO_END - 11;
const int ZER_EXT_DEVICE_INFO_MEMORY_CLOCK_RATE = ZER_EXT_DEVICE_INFO_END - 12;
const int ZER_EXT_DEVICE_INFO_FREE_MEMORY = ZER_EXT_DEVICE_INFO_END - 13;
const int ZER_EXT_DEVICE_INFO_DEVICE_ID = ZER_EXT_DEVICE_INFO_END - 14;
const int ZER_EXT_DEVICE_INFO_IMAGE_MAX_ARRAY_SIZE =
ZER_DEVICE_INFO_IMAGE_MAX_ARRAR_SIZE;

const int ZER_EXT_RESULT_END = 0x1000;
const zer_result_t ZER_EXT_RESULT_ADAPTER_SPECIFIC_ERROR =
zer_result_t(ZER_EXT_RESULT_END - 1);

const int ZER_EXT_USM_CAPS_ACCESS = 1 << 0;
const int ZER_EXT_USM_CAPS_ATOMIC_ACCESS = 1 << 1;
const int ZER_EXT_USM_CAPS_CONCURRENT_ACCESS = 1 << 2;
const int ZER_EXT_USM_CAPS_CONCURRENT_ATOMIC_ACCESS = 1 << 3;

const zer_device_partition_property_flag_t
ZER_EXT_DEVICE_PARTITION_PROPERTY_FLAG_BY_CSLICE =
zer_device_partition_property_flag_t(
ZER_DEVICE_PARTITION_PROPERTY_FLAG_FORCE_UINT32 - 1);

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@pbalcer: please note these UR extensions and make sure there are issues created to follow up

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igchor commented Jan 25, 2023

LGTM. Just FYI, the were some changes in the UR API (mostly ZER prefix was changed to UR) since this code was created: https://github.com/oneapi-src/unified-runtime/blob/main/include/ur_api.h

Is the plan to update the code in llvm to the newest UR version after this PR is merged?

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LGTM. Just FYI, the were some changes in the UR API (mostly ZER prefix was changed to UR) since this code was created: https://github.com/oneapi-src/unified-runtime/blob/main/include/ur_api.h

Is the plan to update the code in llvm to the newest UR version after this PR is merged?

Right. We have to update to the latest UR.
@igchor : would you take an AR to follow up on that after this PR is merged?

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FYI, the were some changes in the UR API (mostly ZER prefix was changed to UR) since this code was created: https://github.com/oneapi-src/unified-runtime/blob/main/include/ur_api.h

Is the plan to update the code in llvm to the newest UR version after this PR is merged?

we are checking out at fd711c920acc4434cb52ff18b078c082d9d7f44d from the UR repo,

set(UNIFIED_RUNTIME_TAG fd711c920acc4434cb52ff18b078c082d9d7f44d)

LGTM. Just FYI, the were some changes in the UR API (mostly ZER prefix was changed to UR) since this code was created: https://github.com/oneapi-src/unified-runtime/blob/main/include/ur_api.h
Is the plan to update the code in llvm to the newest UR version after this PR is merged?

Right. We have to update to the latest UR. @igchor : would you take an AR to follow up on that after this PR is merged?

@smaslov-intel I'm working on integrating with the UR loader (https://github.com/intel/llvm/blob/sycl/sycl/plugins/unified_runtime/CMakeLists.txt#L32). I can do it on the same patch if you'd want me to.

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Is the plan to update the code in llvm to the newest UR version after this PR is merged?

Right. We have to update to the latest UR. @igchor : would you take an AR to follow up on that after this PR is merged?

@smaslov-intel I'm working on integrating with the UR loader (https://github.com/intel/llvm/blob/sycl/sycl/plugins/unified_runtime/CMakeLists.txt#L32). I can do it on the same patch if you'd want me to.

Thanks for volunteering!

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/verify with intel/llvm-test-suite#1544

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The remaining test failure

Failed Tests (1):
SYCL :: Regression/device_num.cpp

Is covered with intel/llvm-test-suite#1544

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+1

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thanks @smaslov-intel . LGTM

Question: if all that we were doing here was to move code from one PI to UR, why were tests failing? just some misses in the porting, or something else major?

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thanks @smaslov-intel . LGTM

Question: if all that we were doing here was to move code from one PI to UR, why were tests failing? just some misses in the porting, or something else major?

@jandres742 : The move from Pi to UR is straightforward.
The complications were related to UR <-> PI translation mostly here here: https://github.com/intel/llvm/pull/8088/files#diff-f1103e5442bf4f71ac0fb3cd9aa969042ee3e864e7b3e8c6f3255b7162ffadfe

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thanks @smaslov-intel . LGTM
Question: if all that we were doing here was to move code from one PI to UR, why were tests failing? just some misses in the porting, or something else major?

@jandres742 : The move from Pi to UR is straightforward. The complications were related to UR <-> PI translation mostly here here: https://github.com/intel/llvm/pull/8088/files#diff-f1103e5442bf4f71ac0fb3cd9aa969042ee3e864e7b3e8c6f3255b7162ffadfe

Note also that the remaining PI interfaces are mostly the same between UR and PI and so will require minimum to no translation.

@smaslov-intel smaslov-intel temporarily deployed to aws February 8, 2023 23:35 — with GitHub Actions Inactive
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
Signed-off-by: Sergey V Maslov <[email protected]>
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@intel/llvm-gatekeepers : please merge this

@againull againull merged commit 33be961 into intel:sycl Feb 9, 2023
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thanks @smaslov-intel . LGTM
Question: if all that we were doing here was to move code from one PI to UR, why were tests failing? just some misses in the porting, or something else major?

@jandres742 : The move from Pi to UR is straightforward. The complications were related to UR <-> PI translation mostly here here: https://github.com/intel/llvm/pull/8088/files#diff-f1103e5442bf4f71ac0fb3cd9aa969042ee3e864e7b3e8c6f3255b7162ffadfe

Note also that the remaining PI interfaces are mostly the same between UR and PI and so will require minimum to no translation.

Working now on updating CMakeLists to user UR loader.

veselypeta pushed a commit to veselypeta/llvm that referenced this pull request Sep 21, 2023
The changes although being large, are just move of the code with
modifications necessary to being able to share it with L0 Plugin.
Signed-off-by: Sergey V Maslov <[email protected]>

---------

Signed-off-by: Sergey V Maslov <[email protected]>
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