[SYCL-MLIR] Merge from intel/llvm sycl branch

.github/workflows/gh_pages.yml

@@ -13,7 +13,7 @@ on:
 
 jobs:
   build:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
     if: github.repository == 'intel/llvm'
     steps:
     - uses: actions/checkout@v3

.github/workflows/sycl_cleanup.yml

@@ -10,7 +10,7 @@ on:
 
 jobs:
   cleanup:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
     steps:
     - uses: actions/github-script@v6
       with:

.github/workflows/sycl_containers.yaml

@@ -25,7 +25,7 @@ jobs:
   base_image_ubuntu2004:
     if: github.repository == 'intel/llvm'
     name: Base Ubuntu 20.04 Docker image
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
     steps:
       - name: Checkout
         uses: actions/checkout@v3
@@ -44,7 +44,7 @@ jobs:
   build_image_ubuntu2004:
     if: github.repository == 'intel/llvm'
     name: Build Ubuntu Docker image
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
     steps:
       - name: Checkout
         uses: actions/checkout@v3
@@ -66,7 +66,7 @@ jobs:
   drivers_image_ubuntu2004:
     if: github.repository == 'intel/llvm'
     name: Intel Drivers Ubuntu 20.04 Docker image
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
     needs: base_image_ubuntu2004
     steps:
       - name: Checkout
@@ -105,7 +105,7 @@ jobs:
   drivers_image_ubuntu2004_unstable:
     if: github.repository == 'intel/llvm'
     name: Intel Drivers (unstable) Ubuntu 20.04 Docker image
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
     needs: base_image_ubuntu2004
     steps:
       - name: Checkout
@@ -136,7 +136,7 @@ jobs:
   base_image_ubuntu2204:
     if: github.repository == 'intel/llvm'
     name: Base Ubuntu 22.04 Docker image
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
     steps:
       - name: Checkout
         uses: actions/checkout@v3
@@ -155,7 +155,7 @@ jobs:
   build_image_ubuntu2204:
     if: github.repository == 'intel/llvm'
     name: Build Ubuntu Docker image
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
     steps:
       - name: Checkout
         uses: actions/checkout@v3
@@ -177,7 +177,7 @@ jobs:
   drivers_image_ubuntu2204:
     if: github.repository == 'intel/llvm'
     name: Intel Drivers Ubuntu 22.04 Docker image
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
     needs: base_image_ubuntu2204
     steps:
       - name: Checkout
@@ -215,7 +215,7 @@ jobs:
   drivers_image_ubuntu2204_unstable:
     if: github.repository == 'intel/llvm'
     name: Intel Drivers (unstable) Ubuntu 22.04 Docker image
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
     needs: base_image_ubuntu2204
     steps:
       - name: Checkout

.github/workflows/sycl_gen_test_matrix.yml

@@ -46,7 +46,7 @@ on:
 jobs:
   test_matrix:
     name: Generate Test Matrix
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
     outputs:
       lts_matrix: ${{ steps.work.outputs.lts_matrix }}
       cts_matrix: ${{ steps.work.outputs.cts_matrix }}

.github/workflows/sycl_stale_issues.yml

@@ -6,7 +6,7 @@ on:
 
 jobs:
   close-issues:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-20.04
     steps:
     - uses: actions/stale@v4
       with:

clang/include/clang/Basic/LangOptions.def

@@ -350,6 +350,7 @@ LANGOPT(ObjCDisableDirectMethodsForTesting, 1, 0,
         "Disable recognition of objc_direct methods")
 LANGOPT(CFProtectionBranch , 1, 0, "Control-Flow Branch Protection enabled")
 LANGOPT(FakeAddressSpaceMap , 1, 0, "OpenCL fake address space map")
+LANGOPT(OpenCLForceVectorABI, 1, 0, "OpenCL vector to scalar coercion disabling")
 ENUM_LANGOPT(AddressSpaceMapMangling , AddrSpaceMapMangling, 2, ASMM_Target, "OpenCL address space map mangling mode")
 LANGOPT(IncludeDefaultHeader, 1, 0, "Include default header file for OpenCL")
 LANGOPT(DeclareOpenCLBuiltins, 1, 0, "Declare OpenCL builtin functions")

clang/include/clang/Driver/Options.td

@@ -6474,6 +6474,9 @@ defm const_strings : BoolOption<"f", "const-strings",
 def fno_bitfield_type_align : Flag<["-"], "fno-bitfield-type-align">,
   HelpText<"Ignore bit-field types when aligning structures">,
   MarshallingInfoFlag<LangOpts<"NoBitFieldTypeAlign">>;
+def fopencl_force_vector_abi : Flag<["-"], "fopencl-force-vector-abi">,
+  HelpText<"Disable vector to scalar coercion for OpenCL">,
+  MarshallingInfoFlag<LangOpts<"OpenCLForceVectorABI">>;
 def ffake_address_space_map : Flag<["-"], "ffake-address-space-map">,
   HelpText<"Use a fake address space map; OpenCL testing purposes only">,
   MarshallingInfoFlag<LangOpts<"FakeAddressSpaceMap">>;

clang/lib/Basic/Targets/NVPTX.cpp

@@ -169,7 +169,8 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
   Builder.defineMacro("__PTX__");
   Builder.defineMacro("__NVPTX__");
   if (Opts.CUDAIsDevice || Opts.OpenMPIsDevice || Opts.SYCLIsDevice) {
-    // Set __CUDA_ARCH__ for the GPU specified.
+    // Set __CUDA_ARCH__ or __SYCL_CUDA_ARCH__ for the GPU specified.
+    // The SYCL-specific macro is used to distinguish the SYCL and CUDA APIs.
     std::string CUDAArchCode = [this] {
       switch (GPU) {
       case CudaArch::GFX600:
@@ -260,7 +261,12 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
       }
       llvm_unreachable("unhandled CudaArch");
     }();
-    Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
+
+    if (Opts.SYCLIsDevice) {
+      Builder.defineMacro("__SYCL_CUDA_ARCH__", CUDAArchCode);
+    } else {
+      Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
+    }
   }
 }
 

clang/lib/CodeGen/TargetInfo.cpp

@@ -100,6 +100,41 @@ Address ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
   return Address::invalid();
 }
 
+static ABIArgInfo classifyOpenCL(QualType Ty, ASTContext &Context) {
+  if (Ty->isVoidType())
+    return ABIArgInfo::getIgnore();
+
+  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
+    Ty = EnumTy->getDecl()->getIntegerType();
+
+  if (const RecordType *RT = Ty->getAs<RecordType>())
+    return ABIArgInfo::getIndirect(Context.getTypeAlignInChars(RT),
+                                   /*ByVal=*/false);
+
+  if (Context.isPromotableIntegerType(Ty))
+    return ABIArgInfo::getExtend(Ty);
+
+  return ABIArgInfo::getDirect();
+}
+
+static bool doOpenCLClassification(CGFunctionInfo &FI, ASTContext &Context) {
+  if (!Context.getLangOpts().OpenCL)
+    return false;
+  if (!Context.getLangOpts().OpenCLForceVectorABI)
+    return false;
+
+  // Use OpenCL classify to prevent coercing.
+  // Vector ABI must be enforced by enabling the corresponding option.
+  // Otherwise, vector types will be coerced to a matching integer
+  // type to conform with ABI, e.g.: <8 x i8> will be coerced to i64.
+  FI.getReturnInfo() = classifyOpenCL(FI.getReturnType(), Context);
+
+  for (auto &Arg : FI.arguments())
+    Arg.info = classifyOpenCL(Arg.type, Context);
+
+  return true;
+}
+
 static llvm::Type *getVAListElementType(CodeGenFunction &CGF) {
   return CGF.ConvertTypeForMem(
       CGF.getContext().getBuiltinVaListType()->getPointeeType());
@@ -1984,6 +2019,10 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
 }
 
 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
+  ASTContext &Context = getContext();
+  if (doOpenCLClassification(FI, Context))
+    return;
+
   CCState State(FI);
   if (IsMCUABI)
     State.FreeRegs = 3;
@@ -3970,6 +4009,9 @@ X86_64ABIInfo::classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
 }
 
 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
+  ASTContext &Context = getContext();
+  if (doOpenCLClassification(FI, Context))
+    return;
 
   const unsigned CallingConv = FI.getCallingConvention();
   // It is possible to force Win64 calling convention on any x86_64 target by
@@ -4427,6 +4469,10 @@ ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
 }
 
 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
+  ASTContext &Context = getContext();
+  if (doOpenCLClassification(FI, Context))
+    return;
+
   const unsigned CC = FI.getCallingConvention();
   bool IsVectorCall = CC == llvm::CallingConv::X86_VectorCall;
   bool IsRegCall = CC == llvm::CallingConv::X86_RegCall;

clang/lib/Driver/ToolChains/SYCL.cpp

@@ -901,17 +901,14 @@ void SYCLToolChain::TranslateTargetOpt(const llvm::opt::ArgList &Args,
     OptNoTriple = A->getOption().matches(Opt);
     if (A->getOption().matches(Opt_EQ)) {
       // Passing device args: -X<Opt>=<triple> -opt=val.
-      if (getDriver().MakeSYCLDeviceTriple(A->getValue()) != getTriple())
+      StringRef GenDevice = SYCL::gen::resolveGenDevice(A->getValue());
+      if (getDriver().MakeSYCLDeviceTriple(A->getValue()) != getTriple() &&
+          GenDevice.empty())
         // Provided triple does not match current tool chain.
         continue;
-      if (getTriple().isSPIR() &&
-          getTriple().getSubArch() == llvm::Triple::SPIRSubArch_gen) {
-        if (Device.empty() && StringRef(A->getValue()).startswith("intel_gpu"))
-          continue;
-        if (!Device.empty() &&
-            getDriver().MakeSYCLDeviceTriple(A->getValue()) == getTriple())
-          continue;
-      }
+      if (Device != GenDevice && getTriple().isSPIR() &&
+          getTriple().getSubArch() == llvm::Triple::SPIRSubArch_gen)
+        continue;
     } else if (!OptNoTriple)
       // Don't worry about any of the other args, we only want to pass what is
       // passed in -X<Opt>

clang/lib/Frontend/CompilerInvocation.cpp

@@ -3928,6 +3928,8 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args,
     }
   }
 
+  Opts.OpenCLForceVectorABI = Args.hasArg(OPT_fopencl_force_vector_abi);
+
   // Check if -fopenmp is specified and set default version to 5.0.
   Opts.OpenMP = Args.hasArg(OPT_fopenmp) ? 50 : 0;
   // Check if -fopenmp-simd is specified.

clang/test/CodeGen/sycl-instrumentation-option.c

@@ -5,7 +5,7 @@
 // RUN: %clang_cc1 -fsycl-instrument-device-code -triple spir64_gen-unknown-unknown %s -emit-llvm -o - 2>&1 | FileCheck %s
 // RUN: %clang_cc1 -fsycl-instrument-device-code -triple spir64_fpga-unknown-unknown %s -emit-llvm -o - 2>&1 | FileCheck %s
 // RUN: %clang_cc1 -fsycl-instrument-device-code -triple spir64_x86_64-unknown-unknown %s -emit-llvm -o - 2>&1 | FileCheck %s
-// CHECK-NOT: error
+// CHECK-NOT: error:
 
 // RUN: not %clang_cc1 -fsycl-instrument-device-code -triple spirv32 -emit-llvm %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK-ERR
 // RUN: not %clang_cc1 -fsycl-instrument-device-code -triple spirv64 -emit-llvm %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK-ERR

clang/test/CodeGenOpenCL/vector-to-scalar-coercion.cl

@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -x cl -triple i686-pc-win32-gnu    -fopencl-force-vector-abi %s -O0 -emit-llvm -o - | FileCheck %s --check-prefix NOCOER
+// RUN: %clang_cc1 -x cl -triple x86_64-unknown-linux -fopencl-force-vector-abi %s -O0 -emit-llvm -o - | FileCheck %s --check-prefix NOCOER
+// RUN: %clang_cc1 -x cl -triple x86_64-pc-win32-gnu  -fopencl-force-vector-abi %s -O0 -emit-llvm -o - | FileCheck %s --check-prefix NOCOER
+
+// RUN: %clang_cc1 -x cl -triple i686-pc-win32-gnu %s    -O0 -emit-llvm -o - | FileCheck %s --check-prefix COER32CL
+// RUN: %clang_cc1 -x cl -triple x86_64-unknown-linux %s -O0 -emit-llvm -o - | FileCheck %s --check-prefix COER64
+// RUN: %clang_cc1 -x cl -triple x86_64-pc-win32-gnu %s  -O0 -emit-llvm -o - | FileCheck %s --check-prefix NOCOER
+
+// RUN: %clang_cc1 -x c  -triple i686-pc-win32-gnu %s    -O0 -emit-llvm -o - | FileCheck %s --check-prefix COER32
+// RUN: %clang_cc1 -x c  -triple x86_64-unknown-linux %s -O0 -emit-llvm -o - | FileCheck %s --check-prefix COER64
+// RUN: %clang_cc1 -x c  -triple x86_64-pc-win32-gnu %s  -O0 -emit-llvm -o - | FileCheck %s --check-prefix NOCOER-C-WIN
+
+typedef unsigned short ushort;
+typedef ushort ushort4 __attribute__((ext_vector_type(4)));
+
+typedef unsigned long ulong;
+typedef ulong ulong4 __attribute__((ext_vector_type(4)));
+
+ulong4 __attribute__((const)) __attribute__((overloadable)) convert_ulong4_rte(ushort4 x)
+{
+  return 1;
+}
+
+// NOCOER:       define {{.*}}<4 x i64> @_Z18convert_ulong4_rteDv4_t(<4 x i16> noundef %{{.*}})
+// NOCOER-C-WIN: define {{.*}}<4 x i32> @_Z18convert_ulong4_rteDv4_t(<4 x i16> noundef %{{.*}})
+// COER32CL:     define {{.*}}<4 x i64> @_Z18convert_ulong4_rteDv4_t(i64 noundef %{{.*}})
+// COER32:       define {{.*}}<4 x i32> @_Z18convert_ulong4_rteDv4_t(i64 noundef %{{.*}})
+// FIXME: <4 x i16> should be coerced to i64 instead of double
+// COER64:       define {{.*}}<4 x i64> @_Z18convert_ulong4_rteDv4_t(double noundef %{{.*}})