Skip to content

[SYCL] Enable SPV_INTEL_fpga_invocation_pipelining_attributes #8827

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 1 commit into from
Mar 29, 2023
Merged

[SYCL] Enable SPV_INTEL_fpga_invocation_pipelining_attributes #8827

merged 1 commit into from
Mar 29, 2023

Conversation

MrSidims
Copy link
Contributor

@MrSidims MrSidims commented Mar 28, 2023 •
edited
Loading

Right now it's only working for FPGA H/W while it should also work for FPGA emulator.

@MrSidims MrSidims requested a review from a team as a code owner March 28, 2023 10:54
@MrSidims MrSidims temporarily deployed to aws March 28, 2023 11:22 — with GitHub Actions Inactive
@MrSidims MrSidims temporarily deployed to aws March 28, 2023 12:42 — with GitHub Actions Inactive
mdtoguchi
mdtoguchi approved these changes Mar 28, 2023
View reviewed changes
Copy link
Contributor

@mdtoguchi mdtoguchi left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

@MrSidims MrSidims requested a review from a team March 29, 2023 19:17
@steffenlarsen steffenlarsen merged commit 3bc0524 into intel:sycl Mar 29, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@mdtoguchi mdtoguchi mdtoguchi approved these changes

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
3 participants
@MrSidims @mdtoguchi @steffenlarsen