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[Clang][LLVM] Implement multi-single vectors MOP4{A/S}
Implement all multi-single {BF/F/S/U/SU/US}MOP4{A/S} instructions in clang and llvm following the acle in https://github.com/ARM-software/acle/pull/381/files. This PR depends on llvm#128854
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6 files changed

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‎clang/include/clang/Basic/arm_sme.td

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -295,6 +295,7 @@ defm SVMOPS : ZAFPOuterProd<"mops">;
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multiclass MOP4<string mode, string za, string t, string i, list<ImmCheck> checks> {
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def _1x1 : Inst<"svmop4" # mode # "[_1x1]" # za # "[_{d}_{d}]", "vidd", t, MergeNone, i # "_1x1", [IsInOutZA, IsStreaming], checks>;
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def _1x2 : Inst<"svmop4" # mode # "[_1x2]" # za # "[_{d}_{d}]", "vid2", t, MergeNone, i # "_1x2", [IsInOutZA, IsStreaming], checks>;
298+
def _2x1 : Inst<"svmop4" # mode # "[_2x1]" # za # "[_{d}_{d}]", "vi2d", t, MergeNone, i # "_2x1", [IsInOutZA, IsStreaming], checks>;
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}
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300301
let SMETargetGuard = "sme2,sme-mop4" in {
@@ -350,6 +351,10 @@ multiclass SUMOP4<string mode, string za, string t, string i, list<ImmCheck> che
350351
"vid2.u", t, MergeNone, "aarch64_sme_sumop4" # mode # i # "_wide_1x2",
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[IsStreaming, IsInOutZA],
352353
checks>;
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def _2x1 : SInst<"svmop4" # mode # "[_2x1]_" # za # "[_{d}_{3}]",
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"vi2u", t, MergeNone, "aarch64_sme_sumop4" # mode # i # "_wide_2x1",
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[IsStreaming, IsInOutZA],
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checks>;
353358
}
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355360
multiclass USMOP4<string mode, string za, string t, string i, list<ImmCheck> checks> {
@@ -361,6 +366,10 @@ multiclass USMOP4<string mode, string za, string t, string i, list<ImmCheck> che
361366
"vid2.x", t, MergeNone, "aarch64_sme_usmop4" # mode # i # "_wide_1x2",
362367
[IsStreaming, IsInOutZA],
363368
checks>;
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def _2x1 : SInst<"svmop4" # mode # "[_2x1]_" # za # "[_{d}_{3}]",
370+
"vi2x", t, MergeNone, "aarch64_sme_usmop4" # mode # i # "_wide_2x1",
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[IsStreaming, IsInOutZA],
372+
checks>;
364373
}
365374

366375
let SMETargetGuard = "sme2,sme-mop4" in {

‎clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c

Lines changed: 304 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,304 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: aarch64-registered-target
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// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
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// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +bf16 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
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// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
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#include <arm_sme.h>
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#ifdef SME_OVERLOADED_FORMS
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#define SME_ACLE_FUNC(A1,A2_UNUSED,A3, A4_UNUSED) A1##A3
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#else
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#define SME_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
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#endif
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// CHECK-LABEL: @test_svmop4a_2x1_za32_s8_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4a_2x1_za32_s8_s8(svint8x2_t zn, svint8_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4a,_2x1,_za32,_s8_s8)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za32_s8_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4s_2x1_za32_s8_s8(svint8x2_t zn, svint8_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4s,_2x1,_za32,_s8_s8)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4a_2x1_za32_u8_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4a_2x1_za32_u8_u8(svuint8x2_t zn, svuint8_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4a,_2x1,_za32,_u8_u8)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za32_u8_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4s_2x1_za32_u8_u8(svuint8x2_t zn, svuint8_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4s,_2x1,_za32,_u8_u8)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4a_2x1_za32_s8_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4a_2x1_za32_s8_u8(svint8x2_t zn, svuint8_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4a,_2x1,_za32,_s8_u8)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za32_s8_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4s_2x1_za32_s8_u8(svint8x2_t zn, svuint8_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4s,_2x1,_za32,_s8_u8)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4a_2x1_za32_u8_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.usmop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4a_2x1_za32_u8_s8(svuint8x2_t zn, svint8_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4a,_2x1,_za32,_u8_s8)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za32_u8_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.usmop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4s_2x1_za32_u8_s8(svuint8x2_t zn, svint8_t zm) __arm_streaming __arm_inout("za") {
86+
SME_ACLE_FUNC(svmop4s,_2x1,_za32,_u8_s8)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4a_2x1_za32_s16_s16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.smop4a.wide.2x1.nxv8i16(i32 1, <vscale x 8 x i16> [[ZN_COERCE0:%.*]], <vscale x 8 x i16> [[ZN_COERCE1:%.*]], <vscale x 8 x i16> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
94+
void test_svmop4a_2x1_za32_s16_s16(svint16x2_t zn, svint16_t zm) __arm_streaming __arm_inout("za") {
95+
SME_ACLE_FUNC(svmop4a,_2x1,_za32,_s16_s16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za32_s16_s16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.smop4s.wide.2x1.nxv8i16(i32 1, <vscale x 8 x i16> [[ZN_COERCE0:%.*]], <vscale x 8 x i16> [[ZN_COERCE1:%.*]], <vscale x 8 x i16> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4s_2x1_za32_s16_s16(svint16x2_t zn, svint16_t zm) __arm_streaming __arm_inout("za") {
104+
SME_ACLE_FUNC(svmop4s,_2x1,_za32,_s16_s16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4a_2x1_za32_u16_u16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.umop4a.wide.2x1.nxv8i16(i32 1, <vscale x 8 x i16> [[ZN_COERCE0:%.*]], <vscale x 8 x i16> [[ZN_COERCE1:%.*]], <vscale x 8 x i16> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4a_2x1_za32_u16_u16(svuint16x2_t zn, svuint16_t zm) __arm_streaming __arm_inout("za") {
113+
SME_ACLE_FUNC(svmop4a,_2x1,_za32,_u16_u16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za32_u16_u16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.umop4a.wide.2x1.nxv8i16(i32 1, <vscale x 8 x i16> [[ZN_COERCE0:%.*]], <vscale x 8 x i16> [[ZN_COERCE1:%.*]], <vscale x 8 x i16> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4s_2x1_za32_u16_u16(svuint16x2_t zn, svuint16_t zm) __arm_streaming __arm_inout("za") {
122+
SME_ACLE_FUNC(svmop4a,_2x1,_za32,_u16_u16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4a_2x1_za32_f16_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.mop4a.wide.2x1.nxv8f16(i32 1, <vscale x 8 x half> [[ZN_COERCE0:%.*]], <vscale x 8 x half> [[ZN_COERCE1:%.*]], <vscale x 8 x half> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4a_2x1_za32_f16_f16(svfloat16x2_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") {
131+
SME_ACLE_FUNC(svmop4a,_2x1,_za32,_f16_f16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za32_f16_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.mop4s.wide.2x1.nxv8f16(i32 1, <vscale x 8 x half> [[ZN_COERCE0:%.*]], <vscale x 8 x half> [[ZN_COERCE1:%.*]], <vscale x 8 x half> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
139+
void test_svmop4s_2x1_za32_f16_f16(svfloat16x2_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") {
140+
SME_ACLE_FUNC(svmop4s,_2x1,_za32,_f16_f16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4a_2x1_za32_bf16_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.mop4a.wide.2x1.nxv8bf16(i32 1, <vscale x 8 x bfloat> [[ZN_COERCE0:%.*]], <vscale x 8 x bfloat> [[ZN_COERCE1:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
148+
void test_svmop4a_2x1_za32_bf16_bf16(svbfloat16x2_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") {
149+
SME_ACLE_FUNC(svmop4a,_2x1,_za32,_bf16_bf16)(1, zn, zm);
150+
}
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// CHECK-LABEL: @test_svmop4s_2x1_za32_bf16_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.mop4s.wide.2x1.nxv8bf16(i32 1, <vscale x 8 x bfloat> [[ZN_COERCE0:%.*]], <vscale x 8 x bfloat> [[ZN_COERCE1:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
157+
void test_svmop4s_2x1_za32_bf16_bf16(svbfloat16x2_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") {
158+
SME_ACLE_FUNC(svmop4s,_2x1,_za32,_bf16_bf16)(1, zn, zm);
159+
}
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// CHECK-LABEL: @test_svmop4a_2x1_za64_s16_s16(
162+
// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.smop4a.za64.wide.2x1.nxv8i16(i32 1, <vscale x 8 x i16> [[ZN_COERCE0:%.*]], <vscale x 8 x i16> [[ZN_COERCE1:%.*]], <vscale x 8 x i16> [[ZM:%.*]])
164+
// CHECK-NEXT: ret void
165+
//
166+
void test_svmop4a_2x1_za64_s16_s16(svint16x2_t zn, svint16_t zm) __arm_streaming __arm_inout("za") {
167+
SME_ACLE_FUNC(svmop4a,_2x1,_za64,_s16_s16)(1, zn, zm);
168+
}
169+
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// CHECK-LABEL: @test_svmop4s_2x1_za64_s16_s16(
171+
// CHECK-NEXT: entry:
172+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.smop4s.za64.wide.2x1.nxv8i16(i32 1, <vscale x 8 x i16> [[ZN_COERCE0:%.*]], <vscale x 8 x i16> [[ZN_COERCE1:%.*]], <vscale x 8 x i16> [[ZM:%.*]])
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// CHECK-NEXT: ret void
174+
//
175+
void test_svmop4s_2x1_za64_s16_s16(svint16x2_t zn, svint16_t zm) __arm_streaming __arm_inout("za") {
176+
SME_ACLE_FUNC(svmop4s,_2x1,_za64,_s16_s16)(1, zn, zm);
177+
}
178+
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// CHECK-LABEL: @test_svmop4a_2x1_za64_u16_u16(
180+
// CHECK-NEXT: entry:
181+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.umop4a.za64.wide.2x1.nxv8i16(i32 1, <vscale x 8 x i16> [[ZN_COERCE0:%.*]], <vscale x 8 x i16> [[ZN_COERCE1:%.*]], <vscale x 8 x i16> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
184+
void test_svmop4a_2x1_za64_u16_u16(svuint16x2_t zn, svuint16_t zm) __arm_streaming __arm_inout("za") {
185+
SME_ACLE_FUNC(svmop4a,_2x1,_za64,_u16_u16)(1, zn, zm);
186+
}
187+
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// CHECK-LABEL: @test_svmop4s_2x1_za64_u16_u16(
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// CHECK-NEXT: entry:
190+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.umop4s.za64.wide.2x1.nxv8i16(i32 1, <vscale x 8 x i16> [[ZN_COERCE0:%.*]], <vscale x 8 x i16> [[ZN_COERCE1:%.*]], <vscale x 8 x i16> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
193+
void test_svmop4s_2x1_za64_u16_u16(svuint16x2_t zn, svuint16_t zm) __arm_streaming __arm_inout("za") {
194+
SME_ACLE_FUNC(svmop4s,_2x1,_za64,_u16_u16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4a_2x1_za64_s16_u16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.sumop4a.za64.wide.2x1.nxv8i16(i32 1, <vscale x 8 x i16> [[ZN_COERCE0:%.*]], <vscale x 8 x i16> [[ZN_COERCE1:%.*]], <vscale x 8 x i16> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4a_2x1_za64_s16_u16(svint16x2_t zn, svuint16_t zm) __arm_streaming __arm_inout("za") {
203+
SME_ACLE_FUNC(svmop4a,_2x1,_za64,_s16_u16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za64_s16_u16(
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// CHECK-NEXT: entry:
208+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.sumop4s.za64.wide.2x1.nxv8i16(i32 1, <vscale x 8 x i16> [[ZN_COERCE0:%.*]], <vscale x 8 x i16> [[ZN_COERCE1:%.*]], <vscale x 8 x i16> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4s_2x1_za64_s16_u16(svint16x2_t zn, svuint16_t zm) __arm_streaming __arm_inout("za") {
212+
SME_ACLE_FUNC(svmop4s,_2x1,_za64,_s16_u16)(1, zn, zm);
213+
}
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// CHECK-LABEL: @test_svmop4a_2x1_za64_u16_s16(
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// CHECK-NEXT: entry:
217+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.usmop4a.za64.wide.2x1.nxv8i16(i32 1, <vscale x 8 x i16> [[ZN_COERCE0:%.*]], <vscale x 8 x i16> [[ZN_COERCE1:%.*]], <vscale x 8 x i16> [[ZM:%.*]])
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// CHECK-NEXT: ret void
219+
//
220+
void test_svmop4a_2x1_za64_u16_s16(svuint16x2_t zn, svint16_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4a,_2x1,_za64,_u16_s16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za64_u16_s16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.usmop4s.za64.wide.2x1.nxv8i16(i32 1, <vscale x 8 x i16> [[ZN_COERCE0:%.*]], <vscale x 8 x i16> [[ZN_COERCE1:%.*]], <vscale x 8 x i16> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4s_2x1_za64_u16_s16(svuint16x2_t zn, svint16_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4s,_2x1,_za64,_u16_s16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4a_2x1_za16_f16_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.mop4a.2x1.nxv8f16(i32 1, <vscale x 8 x half> [[ZN_COERCE0:%.*]], <vscale x 8 x half> [[ZN_COERCE1:%.*]], <vscale x 8 x half> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4a_2x1_za16_f16_f16(svfloat16x2_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4a,_2x1,_za16,_f16_f16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za16_f16_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.mop4s.2x1.nxv8f16(i32 1, <vscale x 8 x half> [[ZN_COERCE0:%.*]], <vscale x 8 x half> [[ZN_COERCE1:%.*]], <vscale x 8 x half> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4s_2x1_za16_f16_f16(svfloat16x2_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4s,_2x1,_za16,_f16_f16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4a_2x1_za32_f32_f32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.mop4a.2x1.nxv4f32(i32 1, <vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]], <vscale x 4 x float> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4a_2x1_za32_f32_f32(svfloat32x2_t zn, svfloat32_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4a,_2x1,_za32,_f32_f32)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za32_f32_f32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.mop4s.2x1.nxv4f32(i32 1, <vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]], <vscale x 4 x float> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4s_2x1_za32_f32_f32(svfloat32x2_t zn, svfloat32_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4s,_2x1,_za32,_f32_f32)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4a_2x1_za64_f64_f64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.mop4a.2x1.nxv2f64(i32 1, <vscale x 2 x double> [[ZN_COERCE0:%.*]], <vscale x 2 x double> [[ZN_COERCE1:%.*]], <vscale x 2 x double> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4a_2x1_za64_f64_f64(svfloat64x2_t zn, svfloat64_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4a,_2x1,_za64,_f64_f64)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za64_f64_f64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.mop4s.2x1.nxv2f64(i32 1, <vscale x 2 x double> [[ZN_COERCE0:%.*]], <vscale x 2 x double> [[ZN_COERCE1:%.*]], <vscale x 2 x double> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4s_2x1_za64_f64_f64(svfloat64x2_t zn, svfloat64_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4s,_2x1,_za64,_f64_f64)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4a_2x1_za16_bf16_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.mop4a.2x1.nxv8bf16(i32 1, <vscale x 8 x bfloat> [[ZN_COERCE0:%.*]], <vscale x 8 x bfloat> [[ZN_COERCE1:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4a_2x1_za16_bf16_bf16(svbfloat16x2_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4a,_2x1,_za16,_bf16_bf16)(1, zn, zm);
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}
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// CHECK-LABEL: @test_svmop4s_2x1_za16_bf16_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.mop4s.2x1.nxv8bf16(i32 1, <vscale x 8 x bfloat> [[ZN_COERCE0:%.*]], <vscale x 8 x bfloat> [[ZN_COERCE1:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]])
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// CHECK-NEXT: ret void
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//
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void test_svmop4s_2x1_za16_bf16_bf16(svbfloat16x2_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") {
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SME_ACLE_FUNC(svmop4s,_2x1,_za16,_bf16_bf16)(1, zn, zm);
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}

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