|
82 | 82 | #cooling-cells = <2>;
|
83 | 83 | };
|
84 | 84 | };
|
| 85 | + |
| 86 | + gpu_opp_table: opp-table { |
| 87 | + compatible = "operating-points-v2"; |
| 88 | + |
| 89 | + opp-125000000 { |
| 90 | + opp-hz = /bits/ 64 <125000000>; |
| 91 | + opp-microvolt = <950000>; |
| 92 | + }; |
| 93 | + opp-250000000 { |
| 94 | + opp-hz = /bits/ 64 <250000000>; |
| 95 | + opp-microvolt = <950000>; |
| 96 | + }; |
| 97 | + opp-285714285 { |
| 98 | + opp-hz = /bits/ 64 <285714285>; |
| 99 | + opp-microvolt = <950000>; |
| 100 | + }; |
| 101 | + opp-400000000 { |
| 102 | + opp-hz = /bits/ 64 <400000000>; |
| 103 | + opp-microvolt = <950000>; |
| 104 | + }; |
| 105 | + opp-500000000 { |
| 106 | + opp-hz = /bits/ 64 <500000000>; |
| 107 | + opp-microvolt = <950000>; |
| 108 | + }; |
| 109 | + opp-666666666 { |
| 110 | + opp-hz = /bits/ 64 <666666666>; |
| 111 | + opp-microvolt = <950000>; |
| 112 | + }; |
| 113 | + }; |
85 | 114 | };
|
86 | 115 |
|
87 | 116 | &apb {
|
|
106 | 135 | interrupt-names = "job", "mmu", "gpu";
|
107 | 136 | clocks = <&clkc CLKID_MALI>;
|
108 | 137 | resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;
|
109 |
| - |
110 |
| - /* |
111 |
| - * Mali clocking is provided by two identical clock paths |
112 |
| - * MALI_0 and MALI_1 muxed to a single clock by a glitch |
113 |
| - * free mux to safely change frequency while running. |
114 |
| - */ |
115 |
| - assigned-clocks = <&clkc CLKID_MALI_0_SEL>, |
116 |
| - <&clkc CLKID_MALI_0>, |
117 |
| - <&clkc CLKID_MALI>; /* Glitch free mux */ |
118 |
| - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, |
119 |
| - <0>, /* Do Nothing */ |
120 |
| - <&clkc CLKID_MALI_0>; |
121 |
| - assigned-clock-rates = <0>, /* Do Nothing */ |
122 |
| - <666666666>, |
123 |
| - <0>; /* Do Nothing */ |
| 138 | + operating-points-v2 = <&gpu_opp_table>; |
124 | 139 | };
|
125 | 140 | };
|
126 | 141 |
|
|
0 commit comments